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Contract analysis / validity-risk-assessment-memo.docx
validity-risk-assessment-memo.docx
1014-00003 · 14 clauses
High · 1 Medium · 3 Standard · 0
I. Executive Summary
I. Executive Summary The purpose of this memorandum is to evaluate the invalidity risks associated with each of the four United States patents that Optiwave Semiconductor Corp. ("OWS" or the "Client") proposes to assert against Lumos Photonics, Inc. ("Lumos") in contemplation of the proposed patent infringement action in the United States District Court for the Northern District of California. This assessment has bee
II. Scope and Methodology
II. Scope and Methodology Patents Evaluated This memorandum evaluates the following four United States patents, each owned by Optiwave Semiconductor Corp.:
1. U.S. Patent No. 10,234,567 ("the '567 Patent") — "Integrated Waveguide Coupler with Ta
1. U.S. Patent No. 10,234,567 ("the '567 Patent") — "Integrated Waveguide Coupler with Tapered Mode Converter for Silicon Photonics Platforms"
2. U.S. Patent No. 10,891,234 ("the '234 Patent") — "Germanium-on-Silicon Photodetector w
2. U.S. Patent No. 10,891,234 ("the '234 Patent") — "Germanium-on-Silicon Photodetector with Graded Buffer Layer for Enhanced Responsivity"
3. U.S. Patent No. 11,045,678 ("the '678 Patent") — "Multi-Channel Optical Transceiver wi
3. U.S. Patent No. 11,045,678 ("the '678 Patent") — "Multi-Channel Optical Transceiver with Integrated Wavelength-Division Multiplexing on Silicon"
4. U.S. Patent No. 11,312,890 ("the '890 Patent") — "Driver Circuit Architecture for High High
⚑ Non-compete / exclusivity restraint
4. U.S. Patent No. 11,312,890 ("the '890 Patent") — "Driver Circuit Architecture for High-Speed Silicon Photonic Mach-Zehnder Modulators" Asserted Claims The specific claims identified for assertion in the pre-suit infringement analyses are as follows: • '567 Patent: Claims 1, 4, 7, 12, and 15 • '234 Patent: Claims 1, 3, 5, 8, and 11 • '678 Patent: Claims 1, 2, 6, 9, and 14 • '890 Patent: Claims 1, 5, 8, and 13 The i
III. U.S. Patent No. 10,234,567 — "Integrated Waveguide Coupler with Tapered Mode Converte Medium
⚑ Notice / time limit to track
III. U.S. Patent No. 10,234,567 — "Integrated Waveguide Coupler with Tapered Mode Converter for Silicon Photonics Platforms" (the '567 Patent) A. Patent Overview The '567 Patent is directed to an integrated optical coupler for coupling light between an optical fiber and a silicon photonic integrated circuit. The patent addresses a fundamental challenge in silicon photonics: the large mode-size mismatch between single
1. Tanaka et al. (U.S. Patent No. 9,456,012)
1. Tanaka et al. (U.S. Patent No. 9,456,012) The most significant prior art reference for the '567 Patent is U.S. Patent No. 9,456,012 ("Tanaka '012"), which was issued on September 6, 2016 — approximately six months prior to the '567 Patent's filing date of March 14, 2017. The Tanaka '012 patent qualifies as prior art under 35 U.S.C. § 102(a)(1) as a United States patent that issued before the effective filing date
2. Other § 102 Prior Art
2. Other § 102 Prior Art Our supplemental prior art search, conducted in coordination with Ted Marchetti and confirmed by the Calderwood & Harkness patent research team, did not identify any other single prior art reference that anticipates all elements of Claim 1 as amended with the "adiabatically coupled" limitation. The general field of tapered waveguide couplers for silicon photonics was well-published by 2017, b
1. Tanaka '012 in Combination with Chen & Liu (2016)
1. Tanaka '012 in Combination with Chen & Liu (2016) The most significant obviousness challenge to the '567 Patent arises from the combination of Tanaka '012 with Chen & Liu, "Segmented Taper Coupler Design for Low-Loss Fiber-to-Chip Coupling," Journal of Photonic Integration, Vol. 14, No. 3, pp. 217–229 (2016). The Chen & Liu article was published in 2016 and thus qualifies as prior art under § 102(a)(1). This refer
IV. U.S. Patent No. 10,891,234 — "Germanium-on-Silicon Photodetector with Graded Buffer La Medium
⚑ Notice / time limit to track
IV. U.S. Patent No. 10,891,234 — "Germanium-on-Silicon Photodetector with Graded Buffer Layer for Enhanced Responsivity" (the '234 Patent) A. Patent Overview The '234 Patent is directed to a germanium-on-silicon (Ge-on-Si) photodetector architecture that employs a graded silicon-germanium (SiGe) buffer layer to reduce threading dislocation density at the germanium/silicon interface, thereby enhancing the responsivity
1. European Patent Application EP 3,234,567 A1 (Nordlicht Photonische GmbH)
1. European Patent Application EP 3,234,567 A1 (Nordlicht Photonische GmbH) The most significant prior art reference for the '234 Patent is European Patent Application EP 3,234,567 A1, filed by Nordlicht Photonische GmbH, a German photonics company based in Munich, Germany. This application was published on August 2, 2017 — approximately one month and six days before the '234 Patent's filing date of September 8, 2017
2. Other § 102 References
2. Other § 102 References The general literature on germanium-on-silicon growth using graded SiGe buffer layers was well developed by 2017. The use of graded buffers to manage the 4.2% lattice mismatch between germanium and silicon had been extensively published in the materials science literature dating back to the early 2000s, with foundational work by groups at MIT, IMEC, and the University of Stuttgart. However,
V. U.S. Patent No. 11,045,678 — "Multi-Channel Optical Transceiver with Integrated Wavelen Medium
⚑ Notice / time limit to track
V. U.S. Patent No. 11,045,678 — "Multi-Channel Optical Transceiver with Integrated Wavelength-Division Multiplexing on Silicon" (the '678 Patent) A. Patent Overview The '678 Patent is directed to a multi-channel optical transceiver that integrates wavelength-division multiplexing ("WDM") functionality monolithically on a single silicon die. WDM is a technique used to increase the bandwidth capacity of optical communi