Contract analysis
Clause-by-clause risk read on any document of the firm. Pick a contract, or open any document from a matter.
Contract analysis / exhibit-c-562-patent.docx
exhibit-c-562-patent.docx
High · 0
Medium · 4
Standard · 0
1. A method for thermal management of a photonic integrated circuit, comprising:
1. A method for thermal management of a photonic integrated circuit, comprising: (a) forming a plurality of micro-channels in a substrate, each micro-channel having a hydraulic diameter of less than 1 mm; (b) positioning the substrate with the plurality of micro-channels adjacent to a photonic integrated circuit substrate having at least one active optical component formed thereon; (c) thermally coupling the micro-ch
2. The method of claim 1, wherein the hydraulic diameter of each micro-channel is in the r
2. The method of claim 1, wherein the hydraulic diameter of each micro-channel is in the range of 50 µm to 500 µm.
3. The method of claim 1, wherein the coolant comprises deionized water or a fluorocarbon-
3. The method of claim 1, wherein the coolant comprises deionized water or a fluorocarbon-based dielectric fluid.
4. The method of claim 1, wherein thermally coupling comprises bonding the micro-channel s
4. The method of claim 1, wherein thermally coupling comprises bonding the micro-channel substrate to the photonic integrated circuit substrate using thermocompression bonding, anodic bonding, or adhesive bonding.
5. The method of claim 1, wherein the photonic integrated circuit comprises a silicon phot
5. The method of claim 1, wherein the photonic integrated circuit comprises a silicon photonics transceiver operating at a data rate of at least 100 Gb/s.
6. An apparatus for thermal management of a photonic integrated circuit, comprising:
6. An apparatus for thermal management of a photonic integrated circuit, comprising: (a) a photonic integrated circuit substrate having at least one active optical component; (b) a micro-channel heat sink comprising a plurality of channels formed in a heat-sink substrate, each channel having a hydraulic diameter of less than 1 mm, the micro-channel heat sink thermally coupled to the photonic integrated circuit substr
7. The apparatus of claim 6, wherein the photonic integrated circuit substrate comprises a
7. The apparatus of claim 6, wherein the photonic integrated circuit substrate comprises a silicon-on-insulator (SOI) wafer.
8. The apparatus of claim 6, wherein the at least one active optical component comprises o
8. The apparatus of claim 6, wherein the at least one active optical component comprises one or more of: a laser, an optical modulator, a photodetector, and a wavelength multiplexer.
9. The apparatus of claim 6, further comprising a thermal interface material disposed betw
9. The apparatus of claim 6, further comprising a thermal interface material disposed between the micro-channel heat sink and the photonic integrated circuit substrate.
10. The apparatus of claim 6, wherein the plurality of channels are arranged in a branchin
10. The apparatus of claim 6, wherein the plurality of channels are arranged in a branching network configuration with a primary manifold channel and a plurality of secondary distribution channels.
11. A method of fabricating an embedded micro-channel heat sink for a photonic integrated
11. A method of fabricating an embedded micro-channel heat sink for a photonic integrated circuit, comprising: (a) providing a silicon substrate; (b) patterning a photolithographic mask on the silicon substrate defining a micro-channel layout; (c) etching the silicon substrate through the photolithographic mask using deep reactive ion etching to form a plurality of micro-channels having hydraulic diameters in the ran
12. The method of claim 11, wherein the deep reactive ion etching produces channels with a
12. The method of claim 11, wherein the deep reactive ion etching produces channels with an aspect ratio of depth to width of at least 5:1.
13. The method of claim 11, wherein passivating comprises forming a thermal oxide layer or
13. The method of claim 11, wherein passivating comprises forming a thermal oxide layer or a silicon nitride layer on the inner surfaces of the micro-channels.
14. The method of claim 11, wherein bonding comprises thermocompression bonding at a tempe
Medium
⚑ Assignment / subcontracting
14. The method of claim 11, wherein bonding comprises thermocompression bonding at a temperature below 300°C to preserve optical waveguide integrity on the photonic integrated circuit die. ASSERTED CLAIMS SUMMARY The following summary is provided for the convenience of the Court and the parties. It does not form part of the patent specification. In the Original Complaint filed in Optiwave Semiconductor Corp. v. Lumic
1. Original Assignment — Inventors to Solara Optics, Inc.
Medium
⚑ Assignment / subcontracting
1. Original Assignment — Inventors to Solara Optics, Inc. Pursuant to employment agreements and invention assignment obligations, each of the named inventors — Dr. Henrik Vasquez, Dr. Mei-Ling Chow, and Dr. Arjun Deshmukh — assigned all right, title, and interest in the invention disclosed in Application No. 14/551,238 (which matured into U.S. Patent No. 9,678,562 B2) to Solara Optics, Inc., a California corporation
2. Asset Purchase Agreement — Solara Optics, Inc. to Optiwave Semiconductor Corp.
Medium
⚑ Assignment / subcontracting
2. Asset Purchase Agreement — Solara Optics, Inc. to Optiwave Semiconductor Corp. On June 15, 2018, Optiwave Semiconductor Corp. ("OWS") entered into an Asset Purchase Agreement ("APA") with Solara Optics, Inc. ("Solara Optics"), pursuant to which OWS acquired from Solara Optics substantially all of its intellectual property assets for a total purchase price of $34.5 million. The assets conveyed under the APA include
3. Dissolution of Solara Optics, Inc.
3. Dissolution of Solara Optics, Inc. Solara Optics, Inc. was dissolved as a California corporation in 2020. The company is now defunct. All intellectual property rights formerly held by Solara Optics were conveyed to OWS prior to dissolution pursuant to the APA described above.
4. Current Owner.
Medium
⚑ Notice / time limit to track
4. Current Owner. The current owner of all right, title, and interest in U.S. Patent No. 9,678,562 B2 is: Optiwave Semiconductor Corp. 4810 Bayside Technology Parkway, Suite 300 Santa Clara, CA 95054 Optiwave Semiconductor Corp. has standing to assert the '562 Patent in the present action. PROSECUTION HISTORY SUMMARY (Relevant Excerpts) The following summary of the prosecution history of U.S. Patent No. 9,678,562 B2