Contract analysis

1. Declaration as to the identity of the inventor (PCT Rule 4.17(i)): The inventors identified in box No. III above are the true and sole inventors of the subject matter of this international application.

2. Declaration as to the applicant's entitlement to claim priority (PCT Rule 4.17(iii)): The Applicant, Optiwave Semiconductor Corp., is entitled to claim priority from U.S. Provisional Application No. 63/297,841 by virtue of assignments executed by each of the named inventors, transferring all right, title, and interest in the invention to the Applicant. Copies of the relevant assignment documents are available upon

3. Declaration of inventorship (equivalent to 37 C.F.R. § 1.63 for US national phase purposes): Each of the named inventors believes himself or herself to be an original inventor of the claimed invention, and the statements made herein are true to the best of each inventor's knowledge and belief. These declarations are submitted to satisfy the requirements for entry into the national phase before the United States Pa

1. PCT Request Form (PCT/RO/101), including all declarations under PCT Rule 4.17, comprising eight (8) pages;

2. Specification (Description), comprising forty-seven (47) pages;

3. Claims, comprising nine (9) pages and including twenty (20) claims;

4. Abstract of the Disclosure, comprising one (1) page;

5. Drawings, comprising ten (10) sheets (Figures 1 through 10);

6. Power of Attorney, executed by Dr. Rajan Menon, CEO of Optiwave Semiconductor Corp., dated January 9, 2023;

7. Priority Document Request under PCT Rule 17.1(a), requesting that the Receiving Office prepare and transmit a certified copy of U.S. Provisional Application No. 63/297,841, filed January 10, 2022, to the International Bureau; and

8. Declarations of Inventorship executed by each of the four named inventors. Priority Claim: This international application claims the benefit of priority under PCT Article 8 and the Paris Convention from U.S. Provisional Application No. 63/297,841, filed January 10, 2022, entitled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture." The entire disclosure of t

1. Overall Modulator Architecture Referring now to Figure 1, an exemplary multi-channel silicon-photonic Mach-Zehnder modulator array 100 according to the present invention is fabricated on a silicon-on-insulator (SOI) substrate 102. The SOI substrate 102 comprises a crystalline silicon device layer 104 having a thickness of approximately 220 nm, disposed on a buried oxide (Box) layer 106 having a thickness of approx

2. Segmented Traveling-Wave Electrode Design Referring now to Figure 2, the traveling-wave electrode structure 200 associated with a single MZI channel 110 is described in greater detail. The electrode structure 200 comprises a plurality of electrode segments 202a, 202b, 202c, 202d (collectively, "electrode segments 202") arranged sequentially along the length of the phase shifter region 120 of the MZI channel 110. I

3. Tapered Impedance-Matching Feature The tapered impedance-matching feature is the central inventive element of the present disclosure. Referring now to Figures 4A, 4B, and 4C, the tapered impedance-matching region 300 disposed between each pair of adjacent electrode segments 202 is described in detail. 3.1 Structure of the Tapered Impedance-Matching Region. Between each pair of adjacent electrode segments (e.g., be

4. Phase Shifter Design Referring again to Figure 3, the PN junction phase shifter 120 is formed within the silicon rib waveguide 118 in each arm of the Mach-Zehnder interferometer. The phase shifter 120 comprises a lateral PN junction formed by selective ion implantation of p-type and n-type dopants into the silicon rib waveguide 118. In a preferred embodiment, the p-type region 302 is formed on one side of the wave

5. Multi-Channel Integration Returning to Figure 1, the multi-channel integration of the modulator array 100 is described. In a first embodiment, the modulator array 100 comprises four MZI channels 110a–110d, providing a four-channel configuration suitable for 800G optical transceivers operating at an aggregate data rate of 4 × 200 Gbaud × 2 bits/symbol (PAM-4) = 1600 Gbit/s gross, or approximately 800 Gbit/s net aft

6. Simulation Results and Performance Data The performance of the tapered-segment electrode architecture of the present invention has been evaluated through detailed electromagnetic and electro-optic simulations, as well as through measurements of prototype devices fabricated on 300 mm SOI wafers. 6.1 Simulated Electro-Optic Bandwidth. Referring to Figure 6, the electro-optic frequency response (S21) was simulated fo

7. Fabrication Process Overview Referring now to Figure 7, the principal fabrication process steps for the segmented traveling-wave electrode structure with tapered impedance-matching regions on an SOI substrate are described. The process flow is compatible with standard CMOS foundry processes and can be implemented on 200 mm or 300 mm SOI wafers. Step 1 — Starting Material: An SOI wafer is provided, comprising a 220