MEMORANDUM

MEMORANDUM
PRIVILEGED & CONFIDENTIAL — ATTORNEY-CLIENT COMMUNICATION / ATTORNEY WORK PRODUCT
TO: Nathaniel Bower, Responsible Partner, Calderwood & Harkness LLP Patricia Langford, General Counsel, Optiwave Semiconductor Corp.
FROM: Dr. Lena Marchetti, Of Counsel, Calderwood & Harkness LLP (Immigration & Global Mobility Practice)
DATE: June 4, 2025
RE: Specialty Occupation Analysis — FY2026 H-1B Cap Petition Positions, Optiwave Semiconductor Corp.
MATTER: SC-OWS-2025-0520-IMM
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I. Purpose and Scope
This memorandum provides a comprehensive legal analysis of the specialty occupation classification for five engineering positions that are the subject of FY2026 H-1B cap-subject petitions to be filed by Calderwood & Harkness LLP on behalf of Optiwave Semiconductor Corp. ("OWS" or the "Company") with United States Citizenship and Immigration Services ("USCIS"). The purpose of this analysis is to evaluate each position against the statutory and regulatory specialty occupation framework established by Section 214(i)(1) of the Immigration and Nationality Act ("INA") and its implementing regulations at 8 C.F.R. § 214.2(h)(4)(ii), to anticipate potential Requests for Evidence ("RFEs"), and to provide recommended evidentiary strategies to ensure the strongest possible filings within the applicable deadline.
The five positions and their respective beneficiaries are as follows:
1.  Photonics Process Engineer — Naveen Sharma (SOC 17-2199, Engineers, All Other)
2.  Analog Design Engineer — Yuki Tanaka (SOC 17-2072, Electronics Engineers, Except Computer)
3.  Verification Engineer — Ekaterina Solovyova (SOC 15-1252, Software Developers)
4.  Thermal Engineer — Ahmed Hassan (SOC 17-2072, Electronics Engineers, Except Computer)
5.  EDA Tools Developer — Min-Jun Lee (SOC 15-1252, Software Developers)
All five beneficiaries were selected in the FY2026 H-1B electronic registration lottery. OWS submitted the electronic registrations on March 7, 2025, and USCIS confirmed the selection of all five registrations on April 1, 2025. Under the applicable filing window, the petitions must be filed no later than June 30, 2025. The petitions will be filed with the USCIS California Service Center, 24000 Avila Road, Laguna Niguel, CA 92677, and each will include a Request for Premium Processing (Form I-907, $2,805 per petition) to secure the fifteen-business-day adjudication timeline.
This analysis addresses each position individually against the four regulatory criteria for specialty occupation classification, evaluates the relative RFE risk for each petition, and provides cross-cutting evidentiary recommendations applicable to all five filings. The memorandum should be read in conjunction with the companion H-1B Cap Petition Strategy Memorandum, the LCA Filing Checklist & Wage Analysis Memorandum, and the Template H-1B Employer Support Letter, all of which are being prepared concurrently under Matter No. SC-OWS-2025-0520-IMM.
This memorandum was prepared under the supervision of Megan Chu, Lead Associate, with research assistance from Derek Okonkwo, Working Associate, both of the Immigration & Global Mobility Practice at Calderwood & Harkness LLP.
II. Legal Framework — Specialty Occupation Classification
A. Statutory Definition — INA § 214(i)(1)
The statutory foundation for the H-1B nonimmigrant visa classification is found in Section 101(a)(15)(H)(i)(b) of the INA, 8 U.S.C. § 1101(a)(15)(H)(i)(b), which provides for the temporary admission of foreign nationals who will be employed in a "specialty occupation." The term "specialty occupation" is defined at INA § 214(i)(1), 8 U.S.C. § 1184(i)(1), which provides:
For purposes of section 101(a)(15)(H)(i)(b), the term "specialty occupation" means an occupation that requires—
(A) theoretical and practical application of a body of highly specialized knowledge, and
(B) attainment of a bachelor's or higher degree in the specific specialty (or its equivalent) as a minimum for entry into the occupation in the United States.
The statutory definition establishes two conjunctive requirements. First, the occupation must involve the theoretical and practical application of a body of "highly specialized knowledge" — that is, knowledge that is both advanced in nature and specialized in scope, beyond what can be acquired through general education or on-the-job training. Second, the occupation must require, as a minimum condition for entry, the attainment of at least a bachelor's degree (or its equivalent) in the "specific specialty" — a term that contemplates a defined field of study directly related to the duties and requirements of the position, as opposed to a general or undifferentiated degree.
It is critical that both prongs of this test are satisfied. An occupation that requires highly specialized knowledge but does not require a bachelor's degree for entry does not qualify. Conversely, an occupation that customarily requires a bachelor's degree but does not involve highly specialized knowledge likewise falls outside the definition. The petitioner bears the burden of demonstrating that the proffered position meets both requirements. See Royal Siam Corp. v. Chertoff, 484 F.3d 139, 147 (1st Cir. 2007); Defensor v. Meissner, 201 F.3d 384, 387 (5th Cir. 2000).
B. Regulatory Criteria — 8 C.F.R. § 214.2(h)(4)(ii)
The implementing regulations at 8 C.F.R. § 214.2(h)(4)(ii) elaborate on the statutory definition by establishing four criteria, at least one of which must be satisfied for a position to qualify as a specialty occupation. The petitioner is not required to demonstrate that all four criteria are met; satisfaction of any single criterion is legally sufficient. However, as a matter of practice and strategic prudence, strong petitions address multiple criteria to provide resilience against potential RFEs and to present the adjudicating officer with multiple independent bases for approval.
The four regulatory criteria are as follows:
Criterion 1 — Normal Minimum Requirement: A baccalaureate or higher degree or its equivalent is normally the minimum requirement for entry into the particular position.
Criterion 2 — Industry Standard or Unique Complexity: The degree requirement is common to the industry in parallel positions among similar organizations, or, in the alternative, an employer may show that its particular position is so complex or unique that it can be performed only by an individual with a degree.
Criterion 3 — Employer's Normal Requirement: The employer normally requires a degree or its equivalent for the position.
Criterion 4 — Specialized and Complex Duties: The nature of the specific duties is so specialized and complex that the knowledge required to perform the duties is usually associated with the attainment of a baccalaureate or higher degree.
Each of these criteria provides a distinct analytical pathway to establishing specialty occupation status. Criterion 1 looks to the general educational norms for the occupation as a whole, drawing primarily on the Department of Labor's Occupational Outlook Handbook ("OOH") and similar authoritative sources. Criterion 2 shifts the focus to either the specific industry in which the petitioning employer operates or the particular characteristics of the position that render it uniquely complex. Criterion 3 examines the employer's own historical hiring practices and internal degree requirements. Criterion 4 focuses on the inherent nature of the position's duties and the level of knowledge required to perform them, regardless of broader occupational or industry norms.
The analysis in Section IV of this memorandum addresses each of the four criteria for each of the five OWS positions, assessing the strength of the evidentiary record under each criterion and identifying the most defensible bases for each petition.
C. Relevant USCIS Policy Guidance
Several sources of USCIS policy guidance bear directly on the specialty occupation analysis for the OWS petitions.
USCIS Policy Manual, Volume 2, Part H. The USCIS Policy Manual, Volume 2, Part H, provides the current authoritative guidance on H-1B specialty occupation adjudications. This guidance consolidated and, in certain respects, superseded prior policy memoranda, including the Neufeld Memorandum (January 8, 2010, "Determining Whether a Position Is a Specialty Occupation") and the February 22, 2018, policy memorandum rescinding the prior deference policy for extension petitions. The Policy Manual establishes that adjudicators must evaluate each petition based on the totality of the evidence, including but not limited to the OOH, employer support letters, expert opinions, comparable job postings, and the specific duties and requirements of the proffered position.
Rescission of Contracts and Itineraries Policy Memorandum. USCIS's rescission of the prior "Contracts and Itineraries" policy memorandum (originally issued February 22, 2018) and adoption of updated adjudication standards have somewhat reduced the documentary burden for petitioners in demonstrating the nature of the work to be performed. Nevertheless, USCIS continues to require a detailed description of the specific duties of the proffered position, and vague or generic job descriptions remain a common basis for RFE issuance. Each OWS petition must include a granular, position-specific job description with percentage-based duty allocations.
*Matter of Simeio Solutions*, 26 I&N Dec. 542 (AAO 2015). This precedent decision of the Administrative Appeals Office established that a petitioner must file an amended H-1B petition with a new or amended Labor Condition Application ("LCA") whenever there is a material change in the terms and conditions of employment, including a change in worksite to a new Metropolitan Statistical Area ("MSA") or area of intended employment. This holding is directly relevant to OWS as a multi-site employer with facilities in three distinct MSAs: San Jose-Sunnyvale-Santa Clara, CA (Site A); Austin-Round Rock-Georgetown, TX (Site B); and Portland-Vancouver-Hillsboro, OR-WA (Site C). Each FY2026 cap petition must accurately identify the primary worksite for the beneficiary and must address any anticipated rotation or travel to secondary worksites. If any beneficiary is expected to be permanently reassigned to a different MSA after the petition is approved, OWS must file an amended petition with a corresponding amended LCA prior to the reassignment.
Increased Scrutiny of Technology Sector Specialty Occupation Claims. USCIS has, in recent adjudication cycles, demonstrated increasing scrutiny of specialty occupation claims in the technology sector, particularly for positions classified under SOC 15-1252 (Software Developers) and, to a lesser extent, SOC 15-1256 (Software Quality Assurance Analysts and Testers). This trend is characterized by RFEs challenging whether proffered positions truly require a degree in a "specific specialty" as opposed to a general bachelor's degree or a degree in any field. The RFEs frequently cite the OOH's language that software developers "usually" need a bachelor's degree in computer science or a "related field," arguing that the breadth of acceptable degree fields undermines the "specific specialty" requirement. This trend is of particular concern for the two OWS positions classified under SOC 15-1252 (Verification Engineer and EDA Tools Developer), and the evidentiary strategies discussed in Sections IV.C and IV.E are designed to address this risk.
D. DOL Occupational Outlook Handbook (OOH) as Evidentiary Source
The Department of Labor's Occupational Outlook Handbook ("OOH") is a primary reference used by USCIS adjudicators to evaluate whether a position typically requires a bachelor's degree for entry. While the OOH is not dispositive — and USCIS has acknowledged that it does not capture the full range of specialized positions within broad occupational categories — it remains the starting point for most adjudicators' analysis, particularly under Criterion 1. The following OOH entries are directly relevant to the five OWS positions:
Electronics Engineers, Except Computer (SOC 17-2072). The OOH states that a "bachelor's degree in electrical engineering, electronics engineering, or a related engineering discipline" is "typically needed" for entry into this occupation. This entry directly supports the specialty occupation classification for the Analog Design Engineer (Tanaka) and the Thermal Engineer (Hassan) positions, both of which are mapped to SOC 17-2072. The OOH's specific reference to a degree in "electrical engineering" or "electronics engineering" establishes a clear "specific specialty" requirement, and this SOC code has historically been one of the least challenged by USCIS adjudicators.
Software Developers (SOC 15-1252). The OOH states that a "bachelor's degree in computer science or a related field" is "typically needed" for entry into this occupation. While this entry supports the general degree requirement, USCIS adjudicators have questioned whether the reference to a "related field" is broad enough to encompass degrees outside of computer science and software engineering, thereby undermining the "specific specialty" argument. This entry is relevant to the Verification Engineer (Solovyova) and EDA Tools Developer (Lee) positions, both classified under SOC 15-1252.
Engineers, All Other (SOC 17-2199). The OOH entry for this residual category cross-references various specialized engineering disciplines, each of which typically requires a bachelor's degree in the relevant engineering specialty. This category encompasses photonics engineers (SOC 17-2199.08), which is the sub-classification applicable to the Photonics Process Engineer (Sharma) position. Because this is a catch-all category, USCIS may scrutinize whether the specific sub-discipline at issue truly requires a degree in a defined specialty, and the petition must provide supplemental evidence establishing the degree requirement for photonics engineering specifically.
Computer Systems Analysts (SOC 15-1211). While not at issue for any of the FY2026 cap petitions, this SOC code is noted for completeness as it relates to positions in OWS's existing H-1B portfolio. No further analysis is required for the current filing cycle.
It is important to note that OOH references should be supplemented with industry-specific evidence in all five petitions. This is particularly critical for the Photonics Process Engineer position (SOC 17-2199) and the two SOC 15-1252 positions, where the OOH may not fully capture the specialized nature of the role as performed in the semiconductor and photonics engineering context. Industry-specific evidence includes, but is not limited to, comparable job postings from peer companies, expert opinion letters, professional association publications (IEEE, SPIE, Semiconductor Industry Association), and academic program descriptions demonstrating the specialized coursework required for each role.
III. Industry Context — Semiconductor and Photonics Engineering
A. Optiwave Semiconductor Corp. — Company Profile
Optiwave Semiconductor Corp. ("OWS") is a Delaware corporation, Federal Employer Identification Number ("FEIN") 82-4931076, headquartered at 4820 Veltrano Parkway, Suite 300, San Jose, California 95134. The Company is classified under North American Industry Classification System ("NAICS") Code 334413 (Semiconductor and Related Device Manufacturing).
OWS specializes in the design and fabrication of photonic integrated circuits ("PICs") for data center interconnect applications. The Company's core product lines include silicon photonic transceivers, co-packaged optics modules, and photonic chiplets designed for next-generation data center switching architectures. OWS's PIC technology addresses the growing demand for high-bandwidth, low-power optical interconnects driven by the expansion of hyperscale data centers, artificial intelligence workloads, and cloud computing infrastructure.
OWS was founded on March 14, 2017, and has grown to approximately 340 full-time employees distributed across three facilities:
•  Site A (Headquarters): 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134 — approximately 210 employees, including engineering, executive leadership, operations, sales, and administrative functions.
•  Site B (Austin Design Center): 2700 West Parmer Lane, Building D, Austin, TX 78727 — approximately 65 employees, primarily focused on IC design, photonic simulation, and EDA tool development.
•  Site C (Portland Test Facility): 8100 Southwest Nimbus Avenue, Suite 120, Beaverton, OR 97008 — approximately 40 employees, focused on photonic device characterization, reliability testing, and quality assurance.
•  Remote employees: Approximately 25 employees work in a fully remote capacity from various locations.
OWS's fiscal year 2024 annual revenue was $187.4 million, as reflected in the Company's audited financial statements prepared by Pendleton Accounting Group LLP. The Company is majority-owned (62.4%) by Crestline Ventures Fund IV, LP, a growth-stage venture capital fund, which acquired its controlling interest on September 15, 2022. The remaining equity is held by the Company's founders, management team, and employee stock option pool.
The Company's Vice President of Engineering is Dr. Yun-Sheng Chen, Ph.D. (University of Illinois Urbana-Champaign, Electrical and Computer Engineering, 2009), who has over sixteen years of experience in photonic integrated circuit design and semiconductor process engineering. Dr. Chen will provide technical attestation letters for each of the five FY2026 cap petitions, detailing the specialized nature of each position, the specific degree requirements, and the technical qualifications of each beneficiary.
OWS's current H-1B portfolio includes fourteen H-1B nonimmigrant workers. With 340 total full-time employees, the Company's H-1B ratio is approximately 4.12%, well below the 15% threshold that would classify OWS as an "H-1B dependent employer" under INA § 212(n)(3)(A). This non-dependent status means that the Company is not subject to the additional attestation requirements applicable to H-1B dependent employers, including the obligation to make good-faith efforts to recruit U.S. workers and the displacement attestation requirements.
B. Industry Degree Requirements
The semiconductor and photonics engineering industry universally requires, as a minimum qualification for engineering positions, a bachelor's degree in electrical engineering, electronics engineering, physics, materials science, computer science, computer engineering, or a closely related STEM field. This industry-wide norm is well documented in professional association publications, industry surveys, and academic program descriptions. The following observations are particularly relevant to OWS's FY2026 petitions:
Photonic Integrated Circuit Design and Fabrication. The design and fabrication of photonic integrated circuits is a highly specialized discipline that draws on multiple areas of advanced engineering and physical science knowledge, including semiconductor physics, quantum optics, electromagnetic theory, waveguide theory, thin-film deposition, photolithography, and cleanroom fabrication processes. Entry into this field requires, at minimum, a bachelor's degree in photonics engineering, electrical engineering, materials science and engineering, or applied physics, with relevant coursework in semiconductor device fabrication, optical engineering, and electromagnetic theory. The degree requirement is further evidenced by the curricula of university programs that produce qualified candidates for these roles, such as the photonics engineering programs at the University of Central Florida (CREOL), the University of Arizona (Wyant College of Optical Sciences), MIT, and IIT Madras.
Analog and Mixed-Signal IC Design. Analog integrated circuit design is among the most specialized sub-disciplines within electrical engineering. Designing high-speed transimpedance amplifiers, laser drivers, clock and data recovery circuits, and serializer/deserializer blocks for photonic transceivers requires deep knowledge of transistor-level circuit design, semiconductor device physics, noise theory, signal integrity, and high-frequency electromagnetic behavior. This knowledge is obtained exclusively through formal degree programs in electrical engineering or electronics engineering with focused coursework in analog circuit design. Industry consensus, reflected in hiring practices at companies such as Dunmore Industries, Marlowe & Co., Westmark Enterprises, Sterling Reach Partners LLC, and other semiconductor manufacturers, uniformly requires at minimum a bachelor's degree in electrical or electronics engineering for analog design positions.
Semiconductor Verification Engineering. Hardware verification engineering is a discipline distinct from general software development, requiring specialized knowledge of hardware description languages (SystemVerilog, VHDL), formal verification methodologies, Universal Verification Methodology ("UVM"), assertion-based verification, timing analysis, power analysis, and the IC design flow from RTL through GDSII. This knowledge is found in electrical engineering, computer engineering, and, to a more limited extent, computer science curricula that include dedicated coursework in digital design, VLSI, and verification methodology. The semiconductor industry uniformly requires at minimum a bachelor's degree in electrical engineering, computer engineering, or computer science with relevant VLSI or digital design coursework for verification engineering roles.
Thermal Engineering for Semiconductor and Photonic Devices. Thermal management of photonic integrated circuits and transceiver modules requires specialized knowledge at the intersection of heat transfer theory, thermodynamics, computational fluid dynamics, finite element analysis, semiconductor device physics, and materials science. This multidisciplinary specialization requires at minimum a bachelor's degree in mechanical engineering, electrical engineering, materials science, or applied physics, with coursework in thermal science and computational methods. The semiconductor industry's thermal engineering discipline is distinct from general HVAC or building thermal engineering, as it focuses on microscale and chip-level thermal phenomena, package-level thermal design, and the thermal behavior of active semiconductor and photonic devices.
Electronic Design Automation (EDA) Tool Development. EDA tool development is a highly specialized niche within the semiconductor industry that requires dual competence in software engineering and semiconductor or photonic design theory. Developing custom algorithms for photonic component placement and routing, waveguide optimization, design rule checking, and process design kit creation requires knowledge of computational geometry, optimization algorithms, data structures, software architecture, and the underlying physics and engineering principles of semiconductor and photonic device design. This combination of competencies is found only in candidates with formal degrees in computer science, electrical engineering, or computer engineering, with coursework spanning both software development and IC/photonic design. The EDA industry (Ridgeline Data Systems, Cobalt Ridge Health IT, Pemberton Enterprises, Severin Solutions) and semiconductor companies with internal EDA teams uniformly require such degrees for EDA development positions.
Industry associations further confirm these degree requirements. The Institute of Electrical and Electronics Engineers ("IEEE"), the International Society for Optics and Photonics ("SPIE"), and the Semiconductor Industry Association ("SIA") all publish standards, conference proceedings, and workforce analyses demonstrating that engineering positions in the semiconductor and photonics sector require a minimum of a bachelor's degree in a specific engineering or physical science discipline.
Recommended Evidence: Derek Okonkwo will compile eight to twelve comparable job postings from peer semiconductor and photonics companies for each of the five positions, demonstrating the industry-wide degree requirement. The target completion date for this compilation is June 10, 2025. Additionally, expert opinion letters from Dr. Yun-Sheng Chen and potentially from one or two external academic experts will reinforce the industry degree standards for each role.
C. Export Control Overlay
It is noted, as contextual background supporting the specialized nature of OWS's engineering positions, that the Company's photonic integrated circuit technology has applications adjacent to defense and national security domains. Certain OWS PIC components are designed for use in defense-related optical communication systems, and the Company maintains a Technology Control Plan ("TCP") in accordance with applicable export control regulations. Deemed export considerations under the Export Administration Regulations ("EAR"), 15 C.F.R. § 734.2(b)(2)(ii), apply to foreign national employees who have access to controlled technology in the course of their employment.
While the export control overlay is not directly part of the specialty occupation analysis under INA § 214(i)(1) and 8 C.F.R. § 214.2(h)(4)(ii), it serves as an additional indicator of the highly specialized and sensitive nature of the engineering work performed at OWS. The fact that the Company's engineering positions involve access to controlled technology that is subject to federal export control regulations underscores the advanced level of specialized knowledge required and supports the argument that these positions cannot be filled by individuals without formal education in the relevant engineering or scientific disciplines. This contextual information may be referenced in the employer support letters, where appropriate, to reinforce the degree requirement argument.
IV. Position-Specific Specialty Occupation Analyses
This section provides a detailed specialty occupation analysis for each of the five OWS positions that are the subject of the FY2026 H-1B cap petitions. Each analysis includes a beneficiary overview, a description of the position and its duties, the minimum degree requirement, an evaluation under each of the four regulatory criteria at 8 C.F.R. § 214.2(h)(4)(ii), and an assessment of potential RFE risks with corresponding mitigation strategies.
A. Photonics Process Engineer — Naveen Sharma
1. Beneficiary Overview
Beneficiary: Naveen Sharma Current Immigration Status: F-1 Optional Practical Training (OPT), authorized through January 15, 2026 Educational Background: Bachelor of Technology (B.Tech.) in Engineering Physics, Indian Institute of Technology Madras ("IIT Madras"), Chennai, India, conferred June 2023 Target Position: Photonics Process Engineer SOC Code: 17-2199 (Engineers, All Other — mapped to Photonics Engineers, 17-2199.08) Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134 (San Jose-Sunnyvale-Santa Clara, CA Metropolitan Statistical Area) Prevailing Wage: $152,506 per year (Level III, SOC 17-2199, San Jose-Sunnyvale-Santa Clara MSA, per DOL Occupational Employment and Wage Statistics data, valid as of the LCA filing date) Proffered Wage: IC3 Engineer level — $175,000 base salary + $30,000 in restricted stock units ("RSUs") per year = $205,000 total annual compensation (exceeds prevailing wage by $52,494, or approximately 34.4%)
2. Position Description and Duties
The Photonics Process Engineer position is housed within OWS's Process Integration Group under the Fabrication Engineering Division. The role is responsible for the design, development, and optimization of photonic integrated circuit fabrication processes, encompassing the full spectrum of semiconductor manufacturing unit processes as applied to silicon photonics platforms. The position requires the application of highly specialized knowledge at the intersection of photonic device physics, semiconductor process engineering, and materials science.
The specific duties of the Photonics Process Engineer include, but are not limited to, the following:
•  Design and optimization of PIC fabrication processes (approximately 35% of duties): Develop and optimize lithography, dry and wet etching, thin-film deposition (PECVD, LPCVD, PVD, ALD), chemical-mechanical planarization (CMP), ion implantation, and thermal processing steps for silicon photonic waveguide fabrication, Mach-Zehnder modulator integration, germanium photodetector formation, and grating coupler patterning. Ensure that process parameters meet the stringent dimensional and uniformity requirements of photonic devices, which typically operate at nanometer-scale tolerances.
•  Process integration and design-for-manufacturability collaboration (approximately 25% of duties): Collaborate with photonic design engineers to translate PIC designs into manufacturable process flows. Evaluate design-for-manufacturability ("DFM") considerations, including process variation impacts on photonic device performance (insertion loss, extinction ratio, responsivity), and provide feedback to design teams to optimize layouts for fabrication yield.
•  Process characterization, yield analysis, and failure analysis (approximately 25% of duties): Conduct process characterization using advanced metrology tools, including scanning electron microscopy ("SEM"), transmission electron microscopy ("TEM"), atomic force microscopy ("AFM"), ellipsometry, optical profilometry, and in-line parametric test structures. Perform statistical yield analysis to identify process excursions, define process windows, and implement statistical process control ("SPC") protocols. Conduct root-cause failure analysis of defective devices using physical failure analysis techniques and correlate findings with process parameters.
•  Documentation and specification development (approximately 15% of duties): Develop and maintain process documentation, including process specifications, work instructions, process flow documents, and equipment qualification protocols for cleanroom fabrication. Ensure documentation compliance with OWS's ISO 9001:2015 quality management system and applicable customer quality requirements.
A detailed Job Description Exhibit with granular percentage-based duty allocations will be attached to the Form I-129 petition.
3. Minimum Degree Requirement
OWS requires, as a minimum qualification for the Photonics Process Engineer position, a bachelor's degree in photonics engineering, electrical engineering, materials science and engineering, applied physics, or a closely related field. A master's degree in one of these disciplines is preferred but not required. The specificity of the acceptable degree fields is critical: the position requires coursework in semiconductor physics, optical engineering or photonics, thin-film processing, semiconductor fabrication, and statistical methods, which are found only in the specified engineering and physical science degree programs. A bachelor's degree in an unrelated field, such as business administration, liberal arts, or even certain engineering disciplines without relevant photonics or semiconductor content (e.g., civil engineering, environmental engineering), would not provide the foundational knowledge necessary to perform the duties of this position.
4. Analysis Under the Four Criteria
Criterion 1 — Normal Minimum Requirement. The OOH entry for Engineers, All Other (SOC 17-2199) indicates that engineers in specialized disciplines within this category typically require a bachelor's degree in an engineering specialty. While the residual nature of the SOC 17-2199 category means that the OOH does not provide a single, detailed occupational profile, it cross-references the specific engineering disciplines encompassed within the category, each of which requires a degree in the relevant specialty. Photonics engineering, classified as SOC 17-2199.08 under the ONET system, is one such specialized discipline. The ONET profile for Photonics Engineers specifies that the typical education required for entry is a bachelor's degree, with the most relevant programs of study being electrical engineering, engineering physics, optics, and photonics. The OWS Photonics Process Engineer position falls squarely within this specialized discipline, and the normal minimum requirement for entry is a bachelor's degree in photonics engineering, electrical engineering, materials science, applied physics, or a closely related field.
To supplement the OOH/O*NET references, the petition should include evidence of degree requirements from university photonics engineering programs (e.g., University of Central Florida CREOL, University of Arizona Wyant College of Optical Sciences, MIT) demonstrating the specialized curriculum that constitutes the minimum educational foundation for photonics process engineering.
Criterion 2 — Industry Standard / Complexity. Comparable photonics and semiconductor companies uniformly require, at minimum, a bachelor's degree in a relevant engineering or physical science discipline for photonics process engineering positions. Companies engaged in silicon photonics, including Hollowell Group (Silicon Photonics Group), Cisco (Ostrander Corporation division), Quillon Industries, Ridgeline & Co., and Sundial Corporation, all require bachelor's degrees in electrical engineering, materials science, applied physics, or a related discipline for equivalent roles. The position is inherently complex: PIC fabrication involves nanoscale process control (waveguide dimensions typically on the order of 220 nm × 500 nm for standard silicon strip waveguides), the integration of optical and electronic components on a single die, and the management of process interactions across dozens of fabrication steps. The complexity is such that it can only be performed by an individual with formal education in the relevant disciplines.
Criterion 3 — Employer's Normal Requirement. OWS has consistently required, since its founding in 2017, at minimum a bachelor's degree in photonics engineering, electrical engineering, materials science and engineering, applied physics, or a closely related field for all photonics process engineering positions. The Company's internal job requisition system and position classification framework specify this degree requirement. Prior incumbents of the Photonics Process Engineer role at OWS have held bachelor's or master's degrees in relevant fields, including: (a) Dr. Sarah Lindholm, M.S. in Electrical Engineering (Stanford University), who served as Photonics Process Engineer from 2018 to 2021; and (b) Rajesh Venkataraman, B.Tech. in Engineering Physics (IIT Bombay), who served in the role from 2021 to 2023. The employer support letter from Dr. Yun-Sheng Chen will attest to this historical requirement.
Criterion 4 — Specialized and Complex Duties. The duties of the Photonics Process Engineer require the direct application of photonic device physics (waveguide theory, mode propagation, optical coupling efficiency), semiconductor processing theory (plasma etch chemistry, thin-film nucleation and growth kinetics, ion implantation range and straggle calculations), statistical process control methodology, and materials science principles (crystal structure, defect physics, interfacial chemistry). This body of knowledge is highly specialized and is attainable only through formal degree programs in photonics engineering, electrical engineering, materials science, or applied physics. An individual without this educational foundation would lack the theoretical framework necessary to understand the physical phenomena governing PIC fabrication processes, let alone to design, optimize, and troubleshoot those processes in a production environment.
5. Potential RFE Risks and Mitigation
Risk 1: SOC 17-2199 as a catch-all category. The primary RFE risk for this position arises from the residual nature of the SOC 17-2199 classification. USCIS adjudicators may view SOC 17-2199 as a catch-all category that encompasses a range engineering specializations, and may challenge whether the specific sub-discipline of photonics process engineering requires a degree in a "specific specialty" as opposed to a general engineering degree. This risk is heightened by the fact that the OOH entry for Engineers, All Other does not provide a detailed occupational profile specific to photonics engineering.
Mitigation: The petition should include: (a) a detailed expert letter from Dr. Yun-Sheng Chen explaining the PIC-specific nature of the role and why the required knowledge base is found only in specific engineering and physical science degree programs; (b) the O*NET profile for Photonics Engineers (17-2199.08), which provides a more granular description of the occupation and its educational requirements; (c) comparable job postings from at least eight peer photonics and semiconductor companies demonstrating that a bachelor's degree in a specific engineering discipline is the uniform industry requirement; (d) publications from IEEE Photonics Society and SPIE demonstrating the specialized nature of photonics engineering as a distinct discipline; and (e) curriculum descriptions from university photonics and optical engineering programs showing the specialized coursework that forms the educational foundation for this role.
Risk 2: Foreign credential evaluation. Mr. Sharma's B.Tech. degree was conferred by the Indian Institute of Technology Madras, a foreign institution. While IIT Madras is internationally recognized as one of India's premier engineering universities, USCIS may require a formal credential evaluation to confirm that the degree is equivalent to a U.S. bachelor's degree in the relevant field.
Mitigation: A credential evaluation from a NACES-member evaluation agency (recommended: Severin Technologies or Thackeray Systems) should be obtained prior to filing, confirming that Mr. Sharma's B.Tech. in Engineering Physics from IIT Madras is equivalent to a U.S. bachelor's degree in engineering physics or applied physics from a regionally accredited institution. The evaluation should include a course-by-course analysis demonstrating coursework in semiconductor physics, photonics, electromagnetic theory, and materials science.
Overall RFE Risk Assessment: MODERATE. The SOC 17-2199 classification presents a moderate level of RFE risk due to its residual nature, but the specialized sub-discipline of photonics engineering and the robust evidentiary strategy outlined above should provide a strong basis for approval.
B. Analog Design Engineer — Yuki Tanaka
1. Beneficiary Overview
Beneficiary: Yuki Tanaka Current Immigration Status: F-1 STEM Optional Practical Training Extension, authorized through July 31, 2026 Educational Background: Master of Science (M.S.) in Electrical Engineering, University of Michigan, Ann Arbor, Michigan, conferred May 2022; Bachelor of Science (B.S.) in Electrical Engineering, University of Michigan, Ann Arbor, Michigan, conferred May 2020 Target Position: Analog Design Engineer SOC Code: 17-2072 (Electronics Engineers, Except Computer) Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134 (San Jose-Sunnyvale-Santa Clara, CA MSA) Prevailing Wage: $157,830 per year (Level III, SOC 17-2072, San Jose-Sunnyvale-Santa Clara MSA, per DOL OES data) Proffered Wage: IC3 Engineer level — $175,000 base salary + $30,000 RSU/year = $205,000 total annual compensation (exceeds prevailing wage by $47,170, or approximately 29.9%)
2. Position Description and Duties
The Analog Design Engineer position is housed within OWS's Analog and Mixed-Signal Design Group under the IC Design Division. The role is responsible for the design, simulation, and verification of high-speed analog and mixed-signal circuits that form the electrical interface between OWS's photonic components and the digital processing elements of photonic transceiver integrated circuits. The position demands deep expertise in transistor-level analog circuit design, semiconductor device physics, and the unique challenges of co-integrating analog electronic circuits with photonic devices.
The specific duties of the Analog Design Engineer include, but are not limited to, the following:
•  High-speed analog circuit design (approximately 40% of duties): Design and optimize transimpedance amplifiers ("TIAs") for germanium photodetectors, laser driver circuits for directly modulated and externally modulated laser sources, clock and data recovery ("CDR") circuits for multi-lane photonic transceivers, and high-speed serializer/deserializer ("SerDes") blocks operating at data rates of 100 Gbps per lane and above. These circuits must meet stringent specifications for bandwidth, noise figure, linearity, power consumption, and jitter performance within the constraints of advanced CMOS and SiGe BiCMOS process technologies.
•  Circuit simulation and analysis (approximately 25% of duties): Perform comprehensive SPICE-level circuit simulation using Cobalt Ridge Health IT Spectre and similar tools, including DC operating point analysis, AC frequency response, transient analysis, noise analysis, Monte Carlo statistical analysis, and corner-case (PVT) simulations. Analyze circuit performance across process, voltage, and temperature variations to ensure robust operation under worst-case conditions.
•  Layout review and post-layout verification (approximately 20% of duties): Review circuit layouts for parasitic effects, electromigration compliance, and design rule conformance. Conduct post-layout extraction and simulation to verify that layout parasitics do not degrade circuit performance below specifications. Collaborate with layout engineers and the physical design team to optimize floorplanning and signal routing for critical analog blocks.
•  Electro-optical co-optimization (approximately 15% of duties): Collaborate with photonics design and digital design teams to co-optimize the performance of the overall electro-optical system. Participate in system-level link budget analysis, develop models for photonic-electronic interface characterization, and contribute to the specification of performance targets for analog circuit blocks based on system-level requirements.
3. Minimum Degree Requirement
OWS requires, as a minimum qualification for the Analog Design Engineer position, a bachelor's degree in electrical engineering, electronics engineering, or a closely related engineering field with coursework in analog circuit design, semiconductor device physics, and signal processing. A master's degree in electrical engineering with a specialization in analog or mixed-signal IC design is preferred. The degree requirement is narrowly defined: the position requires a formal engineering education that includes advanced coursework in circuit theory, transistor-level design, semiconductor device modeling (MOSFET, BJT, HBT), feedback systems, noise analysis, and high-frequency circuit design. These courses are found almost exclusively in accredited electrical engineering and electronics engineering degree programs.
4. Analysis Under the Four Criteria
Criterion 1 — Normal Minimum Requirement. The OOH entry for Electronics Engineers, Except Computer (SOC 17-2072) explicitly states that a "bachelor's degree in electrical engineering, electronics engineering, or a related engineering discipline" is "typically needed" for entry into this occupation. This is among the clearest and most unequivocal degree requirements in the OOH, and it directly establishes that a baccalaureate degree in a specific engineering specialty is the normal minimum requirement for entry into the particular position. The Analog Design Engineer position at OWS is a paradigmatic example of an electronics engineering role, involving the design of analog integrated circuits for electronic systems. There is no ambiguity regarding the degree requirement, and this criterion is strongly satisfied.
Criterion 2 — Industry Standard / Complexity. The semiconductor industry uniformly requires, at minimum, a bachelor's degree in electrical engineering or electronics engineering for analog IC design positions. This requirement is universal across companies of all sizes, from major integrated device manufacturers (Hollowell Group, Northgate & Co., Thackeray Holdings design centers) to fabless semiconductor companies (Quillon & Co., Dunmore Industries, Marlowe & Co., Pinnacle & Co.) to photonics companies (Quillon Industries, Ridgeline & Co., Sundial Corporation). Job postings from these and comparable companies consistently specify "BSEE" or "BS in Electrical Engineering" as the minimum educational requirement for analog design roles. The degree requirement is driven by the inherent complexity of analog IC design, which demands mastery of semiconductor device physics at the transistor level, advanced circuit theory, and the mathematical foundations of signal processing and control systems — knowledge that is acquired only through formal engineering degree programs.
Criterion 3 — Employer's Normal Requirement. OWS has required, since its inception in 2017, at minimum a bachelor's degree in electrical engineering or electronics engineering for all analog design engineering positions. The Company's internal hiring records and position classification framework document this requirement. All prior and current incumbents of analog design roles at OWS hold at minimum a bachelor's degree in electrical engineering, and the majority hold advanced degrees (M.S. or Ph.D.) in the same discipline.
Criterion 4 — Specialized and Complex Duties. The duties of the Analog Design Engineer require mastery of advanced circuit theory (Kirchhoff's laws, Thevenin and Claveth equivalences applied to complex multi-stage amplifier topologies), semiconductor device modeling (small-signal and large-signal MOSFET models, noise models, device scaling effects), high-frequency electromagnetic theory (transmission line effects, impedance matching, electromagnetic coupling), and feedback system stability analysis (Bode plots, phase margin, gain margin). Designing a transimpedance amplifier for a germanium photodetector operating at 100 Gbps per lane, for example, requires the designer to simultaneously optimize bandwidth, transimpedance gain, input-referred noise current density, group delay variation, and power consumption within the constraints of a specific CMOS or BiCMOS process technology — a task that is impossible without the theoretical foundations provided by a formal electrical engineering education. The specialized and complex nature of these duties is such that the knowledge required to perform them is inextricably associated with the attainment of a baccalaureate or higher degree in electrical or electronics engineering.
5. Potential RFE Risks and Mitigation
This position presents a strong specialty occupation classification with low RFE risk. The SOC 17-2072 classification for Electronics Engineers has a clear, unambiguous OOH degree requirement, and analog IC design is a well-recognized specialty within electrical engineering that has consistently been approved as a specialty occupation by USCIS. The beneficiary, Ms. Tanaka, holds both a B.S. and an M.S. in Electrical Engineering from the University of Michigan, one of the nation's preeminent engineering programs, providing an unassailable educational qualification.
Mitigation (standard): A standard employer support letter from Dr. Yun-Sheng Chen describing the specific duties of the position and the degree requirement, supplemented by three to five comparable job postings from peer semiconductor companies, should be sufficient to support this petition. No extraordinary evidentiary measures are anticipated.
Overall RFE Risk Assessment: LOW.
C. Verification Engineer — Ekaterina Solovyova
1. Beneficiary Overview
Beneficiary: Ekaterina Solovyova Current Immigration Status: F-1 STEM Optional Practical Training Extension, authorized through May 15, 2026 Educational Background: Master of Science (M.S.) in Electrical Engineering and Computer Sciences, University of California, Berkeley, conferred May 2022; Bachelor of Science (B.S.) in Electrical Engineering and Computer Sciences, University of California, Berkeley, conferred May 2020 Target Position: Verification Engineer SOC Code: 15-1252 (Software Developers) Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134 (San Jose-Sunnyvale-Santa Clara, CA MSA) Prevailing Wage: $168,272 per year (Level III, SOC 15-1252, San Jose-Sunnyvale-Santa Clara MSA, per DOL OES data) Proffered Wage: IC3 Engineer level — $175,000 base salary + $30,000 RSU/year = $205,000 total annual compensation (exceeds prevailing wage by $36,728, or approximately 21.8%)
2. Position Description and Duties
The Verification Engineer position is housed within OWS's Design Verification Group under the IC Design Division. The role is responsible for developing and executing comprehensive verification strategies for OWS's photonic integrated circuit and transceiver ASIC designs, ensuring functional correctness, timing closure, power compliance, and design rule conformance prior to tape-out. The position requires specialized knowledge of semiconductor verification methodology, hardware description languages, formal methods, and the IC design flow — knowledge that is fundamentally distinct from general software development.
The specific duties of the Verification Engineer include, but are not limited to, the following:
•  Verification planning and testbench development (approximately 35% of duties): Develop comprehensive verification plans based on design specifications, identifying verification goals, coverage targets, and test scenarios. Architect and implement verification testbenches using SystemVerilog and Universal Verification Methodology ("UVM"), including the development of UVM agents, sequencers, drivers, monitors, scoreboards, and virtual sequences. Design testbench architectures that support both directed testing and constrained-random stimulus generation for thorough exploration of the design state space.
•  Constrained-random testing and functional coverage (approximately 25% of duties): Create constrained-random test environments that systematically exercise design functionality across a broad range of input combinations and corner cases. Develop functional coverage models using SystemVerilog covergroups and coverpoints to measure verification completeness and identify coverage holes. Implement assertion-based verification ("ABV") frameworks using SystemVerilog Assertions ("SVA") to continuously monitor design behavior during simulation and flag protocol violations, timing errors, and functional bugs in real time.
•  RTL-to-GDSII verification (approximately 25% of duties): Perform gate-level simulation following logic synthesis to verify functional equivalence between the RTL description and the synthesized netlist. Conduct static timing analysis ("STA") using industry-standard tools to verify timing closure across all process-voltage-temperature corners. Perform power analysis to ensure compliance with power budgets and identify potential power integrity issues. Execute design rule checking ("DRC") and layout versus schematic ("LVS") verification to confirm physical layout conformance with foundry design rules and electrical connectivity.
•  Bug triage and tape-out readiness (approximately 15% of duties): Collaborate with design and physical implementation teams to investigate, classify, and resolve verification failures. Participate in bug triage meetings, track defect resolution progress, and maintain verification closure metrics. Provide sign-off on verification readiness prior to tape-out milestones, certifying that all functional and physical verification criteria have been met.
3. Minimum Degree Requirement
OWS requires, as a minimum qualification for the Verification Engineer position, a bachelor's degree in electrical engineering, computer engineering, computer science, or a closely related field with specialization in digital design verification, VLSI design, or semiconductor verification methodologies. A master's degree in one of these disciplines is preferred. The degree requirement specifically contemplates a curriculum that includes coursework in digital logic design, hardware description languages (SystemVerilog, VHDL), computer architecture, VLSI design, verification methodology, formal methods, and semiconductor device fundamentals. While a computer science degree may satisfy the minimum requirement, it must include sufficient hardware-oriented coursework to provide the foundational knowledge necessary for semiconductor verification engineering.
4. Analysis Under the Four Criteria
Criterion 1 — Normal Minimum Requirement. The OOH entry for Software Developers (SOC 15-1252) states that a bachelor's degree in computer science or a related field is "typically needed" for entry into this occupation. This satisfies the baseline requirement that a bachelor's degree is the normal minimum for the occupation. However, USCIS has, in recent adjudication practice, occasionally challenged whether the broad category of "Software Developers" encompasses positions that accept such a wide range of degree fields as to undermine the "specific specialty" requirement. The petition must therefore distinguish the Verification Engineer role from general software development, emphasizing that it is a semiconductor engineering discipline that requires specialized hardware-oriented knowledge beyond what is taught in a general computer science or software engineering curriculum. The OOH's reference to a "related field" should be interpreted in the context of the specific position — here, the "related fields" are electrical engineering and computer engineering, not unrelated disciplines such as information technology or management information systems.
Criterion 2 — Industry Standard / Complexity. In the semiconductor industry, verification engineering is recognized as a distinct discipline with its own body of knowledge, professional organizations, and career pathways. It is categorically different from general-purpose software development, although it shares certain software engineering skills (e.g., programming in SystemVerilog, which is both a hardware description language and a verification language). The industry standard for verification engineering positions at semiconductor companies uniformly requires, at minimum, a bachelor's degree in electrical engineering, computer engineering, or computer science with relevant VLSI or digital design coursework. Job postings from peer semiconductor companies — including Hollowell Group, Thackeray & Co., Stonefield Holdings, Quillon & Co., Dunmore Industries, Marlowe & Co., and others — consistently specify this degree requirement for verification engineering roles. The position is complex by nature, requiring the engineer to understand the semiconductor design at a level sufficient to develop verification strategies that thoroughly test the design's functionality, timing, and power behavior.
Criterion 3 — Employer's Normal Requirement. OWS requires, and has always required since its inception, at minimum a bachelor's degree in electrical engineering, computer engineering, or computer science with specific coursework in VLSI design and verification methodology for all verification engineering positions. The Company's hiring records demonstrate that all prior and current verification engineers hold degrees in one of these three disciplines, with the majority having completed dedicated VLSI or digital design verification coursework. This consistent historical practice establishes the employer's normal requirement.
Criterion 4 — Specialized and Complex Duties. The duties of the Verification Engineer require the application of highly specialized knowledge that is fundamentally different from general software development. Specifically, the role requires: (a) deep knowledge of semiconductor design concepts, including digital logic design, computer architecture, and the IC design flow from RTL through physical implementation; (b) mastery of hardware description and verification languages (SystemVerilog, UVM), which are specialized languages used exclusively in the semiconductor industry and are not part of general software development curricula; (c) knowledge of formal verification methods, including model checking and equivalence checking, which require a mathematical foundation in formal logic and automata theory applied to hardware systems; (d) understanding of static timing analysis, which requires knowledge of semiconductor device timing models, clock domain crossing, and setup/hold time constraints; and (e) understanding of power analysis, which requires knowledge of dynamic and static power dissipation mechanisms in CMOS circuits. This body of knowledge is only attainable through formal degree programs in electrical engineering, computer engineering, or computer science with specialized hardware-oriented coursework.
5. Potential RFE Risks and Mitigation
Elevated Risk. The SOC 15-1252 (Software Developers) classification is a frequent target for USCIS RFEs challenging whether a "specific specialty" degree is required for the position. USCIS adjudicators reviewing positions under this SOC code may apply a generalized view that software development broadly does not require a degree in a single specific field, pointing to the OOH's reference to degrees in "computer science or a related field" as evidence that the occupation accepts a range of degree fields. If the adjudicator does not appreciate the distinction between general software development and semiconductor verification engineering, the petition may receive an RFE questioning the degree specificity.
Mitigation Strategy:
(a) Emphasize the hardware/semiconductor context. The employer support letter from Dr. Yun-Sheng Chen must clearly distinguish the Verification Engineer role from general software development, explaining that the position is fundamentally a semiconductor engineering role that uses software-like tools (SystemVerilog, UVM) to verify hardware designs. The letter should explain that a general software developer without knowledge of digital logic design, VLSI, semiconductor device physics, and the IC design flow would be unable to perform the duties of the position.
(b) Include a detailed expert declaration. Dr. Yun-Sheng Chen's letter should function as an expert declaration, providing a technical explanation of why general software development skills are insufficient and why the specific educational background (EE, CE, or CS with hardware coursework) is required. Consideration should be given to obtaining an additional expert opinion from an external academic expert in VLSI design or verification methodology (e.g., a professor from UC Berkeley's EECS Department or Stanford's Electrical Engineering Department).
(c) Provide curriculum comparisons. Include course catalog excerpts from relevant university programs showing that the required coursework for verification engineering — hardware description languages (HDL), digital logic design, VLSI design, verification methodology, computer architecture — is found primarily in electrical engineering and computer engineering programs. Demonstrate that a general computer science degree without these specific courses would not prepare a graduate for the Verification Engineer role.
(d) Compile comparable job postings. Derek Okonkwo should compile eight to twelve comparable job postings from peer semiconductor companies for verification engineering roles, demonstrating that the industry uniformly requires a degree in electrical eng