UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION
OPTIWAVE SEMICONDUCTOR CORP.,
Plaintiff,
v.
LUMOS PHOTONICS, INC.,
Defendant.
Case No. 5:22-cv-03417-EJD
Hon. Edward J. Torvelis
DECLARATION OF DR. HAROLD WHITFIELD, Ph.D. IN SUPPORT OF PLAINTIFF OPTIWAVE SEMICONDUCTOR CORP.'S OPENING CLAIM CONSTRUCTION BRIEF
Filed: December 5, 2022
I. INTRODUCTION AND PURPOSE OF DECLARATION
1. I, Dr. Harold Whitfield, Ph.D., submit this declaration in support of Plaintiff Optiwave Semiconductor Corp.'s ("OWS") Opening Claim Construction Brief. I have been retained by Calderwood & Harkness LLP, counsel for OWS, to provide expert technical opinions regarding the construction of disputed claim terms in U.S. Patent Nos. 10,234,567 ("the '567 Patent"); 10,891,234 ("the '234 Patent"); 11,045,678 ("the '678 Patent"); and 11,312,890 ("the '890 Patent") (collectively, the "patents-in-suit").
2. The purpose of this declaration is to opine on the understanding of a person of ordinary skill in the art ("POSITA") with respect to the eleven (11) disputed claim terms identified in the Joint Claim Construction and Prehearing Statement filed on October 14, 2022, pursuant to Patent Local Rule 4-3. My opinions address the plain and ordinary meaning of those disputed terms as a POSITA would have understood them as of the respective filing dates of the patents-in-suit.
3. This declaration is offered in support of OWS's Opening Claim Construction Brief filed on December 5, 2022.
4. In forming the opinions set forth in this declaration, I have drawn upon my extensive education, research, and consulting experience in the field of integrated silicon photonics, spanning more than thirty-five years. I have reviewed the patents-in-suit, their complete prosecution histories, relevant prior art, technical literature, deposition transcripts, and other materials described in Section IV below and listed in Appendix B. My opinions are based on this review, together with my knowledge and experience as a researcher, professor, and technical consultant in the field of photonic integrated circuits and silicon photonics.
5. I am being compensated for my time in connection with this matter at my standard consulting rate, as described further below. My compensation is in no way contingent on the outcome of this litigation or the opinions I express herein.
6. I reserve the right to supplement or amend this declaration as additional information becomes available, including but not limited to responsive expert reports, additional deposition testimony, and any supplemental materials produced by either party.
II. QUALIFICATIONS AND BACKGROUND
A. Education
7. I received my Ph.D. in Electrical Engineering from the University of California, Berkeley, in 1987. My doctoral research focused on integrated photonic circuits, and my dissertation, entitled "Coupled-Mode Analysis and Design of Vertically Integrated III-V/Silicon Waveguide Structures for Monolithic Optoelectronic Receivers," addressed the theoretical and experimental aspects of integrating compound semiconductor optical components with silicon-based electronic circuits—a topic that presaged the development of the modern silicon photonics field.
8. Prior to my doctoral studies, I received a Master of Science degree in Electrical Engineering from the Massachusetts Institute of Technology in 1983, where my master's thesis focused on the design and characterization of directional coupler structures in lithium niobate for optical switching applications. I received my Bachelor of Science degree in Electrical Engineering, summa cum laude, from the Georgia Institute of Technology in 1981.
B. Academic Positions
9. I am Professor Emeritus in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara ("UCSB"), where I served on the faculty from 1988 until my retirement from active teaching in 2019. During my tenure at UCSB, I held the endowed William S. Friedman Chair in Photonic Engineering from 2004 through 2019.
10. My academic career spans more than three decades of research and teaching in the fields of integrated photonics, silicon photonics, optoelectronic device design, and high-speed optical communication systems. At UCSB, I directed the Integrated Photonics Research Laboratory, where my research group conducted pioneering work on waveguide coupling structures, germanium-on-silicon photodetectors, silicon optical modulators, and photonic integrated circuit architectures for data communications and telecommunications applications.
11. Over the course of my academic career, I supervised twenty-seven doctoral dissertations and forty-one master's theses, the majority of which addressed topics directly relevant to the technologies at issue in this litigation. I taught graduate-level courses in "Silicon Photonics" (ECE 245), "Optoelectronic Devices and Systems" (ECE 230), "Guided-Wave Optics" (ECE 228), and "Advanced Semiconductor Device Physics" (ECE 225), among others.
12. I held visiting professorships at Imperial College London (2002–2003) and the Technical University of Denmark (2010), where I collaborated on research programs in photonic integrated circuits and high-speed optical interconnects.
C. Professional Affiliations and Recognition
13. Over the course of my career, I have authored or co-authored more than two hundred (200) publications in peer-reviewed journals and conference proceedings in the field of integrated photonics. These publications address a wide range of topics directly relevant to the patents-in-suit, including:
(a) waveguide coupling and mode conversion, including taper design, adiabatic transitions, and fiber-to-chip coupling efficiency optimization;
(b) germanium-on-silicon photodetector design, including buffer layer engineering, defect mitigation, and high-responsivity detector architectures;
(c) integrated optical transceivers, including multi-channel wavelength-division multiplexing on silicon photonic platforms, arrayed waveguide grating design, and ring resonator-based multiplexers;
(d) modulator driver architectures, including co-integration of CMOS electronics with silicon photonic Mach-Zehnder modulators and pre-emphasis equalization techniques for high-baud-rate operation.
14. Representative publications of direct relevance to the subject matter of this declaration include:
• H. Whitfield, J.R. Kowalski, and M.A. Torres, "Adiabatic Mode Conversion in Vertically Coupled Silicon-Silicon Nitride Waveguide Structures," Journal of Lightwave Technology, Vol. 28, No. 14, pp. 2045–2055 (2010).
• H. Whitfield and S. Bhargava, "Design Optimization of Inverse Taper Couplers for Low-Loss Fiber-to-Chip Coupling in SOI Photonics," Optics Express, Vol. 20, No. 12, pp. 13455–13469 (2012).
• T.C. Nguyen, H. Whitfield, and P.L. Alvarez, "Germanium-on-Silicon Photodetectors with Graded SiGe Buffer Layers: Impact of Composition Profile on Responsivity and Dark Current," IEEE Photonics Technology Letters, Vol. 26, No. 18, pp. 1834–1837 (2014).
• H. Whitfield, R. Yamamoto, and A.K. Singh, "Monolithically Integrated 8-Channel DWDM Transceiver on a Silicon Photonic Platform," Optica, Vol. 3, No. 7, pp. 712–720 (2016).
• H. Whitfield and D. Petrov, "Co-Integration of CMOS Pre-Emphasis Driver Circuits with Silicon Photonic Mach-Zehnder Modulators for 56 Gbaud PAM-4 Operation," IEEE Journal of Solid-State Circuits, Vol. 53, No. 2, pp. 432–445 (2018).
15. I am a Fellow of the Institute of Electrical and Electronics Engineers ("IEEE"), elected in 2007 "for contributions to integrated photonic circuit design and silicon photonics." I am also a Fellow of Optica (formerly the Optical Society of America, or "OSA"), elected in 2005. I am a Senior Member of the International Society for Optics and Photonics ("SPIE").
16. I have received multiple awards for my research contributions, including the IEEE Photonics Society Engineering Achievement Award (2015), the Optica Joseph Fraunhofer Award/Robert M. Burley Prize (2012), and the UCSB Academic Senate Distinguished Teaching Award (2009).
17. I have served on the editorial boards of the Journal of Lightwave Technology, IEEE Photonics Technology Letters, and Optics Express. I have served as a technical program committee member or chair for numerous international conferences, including the Optical Fiber Communication Conference (OFC), the Conference on Lasers and Electro-Optics (CLEO), and the IEEE International Conference on Group IV Photonics.
D. Current Affiliation
18. Since my retirement from UCSB in 2019, I have been the Principal of Whitfield Technical Consulting Group, Inc., headquartered at 530 Lytton Avenue, Suite 210, Palo Alto, California 94301. Through my consulting practice, I provide technical expert services in patent litigation, technology assessment, and due diligence in the fields of photonics, semiconductors, and optoelectronics.
E. Prior Expert Testimony Experience
19. I have been retained as a technical expert in patent litigation matters on numerous occasions. In the past five years, I have been deposed nine (9) times and have provided trial testimony in federal court on four (4) occasions. The subject matters of these prior engagements have included silicon photonics device design, optoelectronic packaging, semiconductor fabrication processes, integrated circuit architectures for optical communications, and related technologies. A complete listing of cases in which I have provided expert testimony in the past four years is included in my curriculum vitae, attached hereto as Appendix A.
F. Compensation
20. I am being compensated at the rate of $875 per hour for my consulting and expert services in this matter. This rate is consistent with my standard professional consulting rate. My compensation is not contingent on the outcome of this litigation or on the substance of the opinions I express herein.
III. DEFINITION OF A PERSON OF ORDINARY SKILL IN THE ART
21. The patents-in-suit relate to the field of silicon photonics integrated circuits for high-speed optical communication. Specifically, the claimed inventions address: (a) waveguide coupling structures with tapered mode converters; (b) germanium-on-silicon photodetectors with graded buffer layers; (c) multi-channel optical transceivers with integrated wavelength-division multiplexing; and (d) driver circuit architectures for silicon photonic Mach-Zehnder modulators.
22. Based on my review of the patents-in-suit, the prior art of record, and my experience in the field, I believe that a person of ordinary skill in the art at the time of the inventions would be a person holding at least a Master's degree (or the equivalent) in Electrical Engineering, Applied Physics, or a closely related discipline, with at least three to five (3–5) years of practical experience in the design, fabrication, or characterization of silicon photonics devices, including familiarity with waveguide structures, photodetectors, optical modulators, and photonic integrated circuit ("PIC") architectures for data communications and telecommunications applications.
23. Alternatively, a person of ordinary skill in the art could be an individual holding a Ph.D. in Electrical Engineering, Applied Physics, Materials Science, or a related field with at least one to two (1–2) years of industry or academic research experience in silicon photonics.
24. Additional education or training could compensate for less practical experience, and vice versa. The definition I propose is not rigid; individuals with various combinations of education and experience may qualify as persons of ordinary skill in the art.
25. A POSITA at the relevant time would be familiar with standard texts in the field, including works such as Silicon Photonics Design by Chrostowski and Hochberg (Cambridge University Press, 2015), Handbook of Silicon Photonics by Vivien and Pavesi (Aldermere Partners LLC, 2013), and Photonic Devices by Liu (Cambridge University Press, 2005). A POSITA would also be familiar with publications in leading journals such as the Journal of Lightwave Technology, Optics Express, Optica, IEEE Photonics Technology Letters, IEEE Journal of Selected Topics in Quantum Electronics, and IEEE Transactions on Circuits and Systems, as well as conference proceedings from OFC, CLEO, and the European Conference on Optical Communication (ECOC). A POSITA would also be aware of the state of the art as of the relevant filing dates of the patents-in-suit, which range from March 14, 2017, through November 15, 2018.
26. Unless otherwise stated, my opinions in this declaration are offered from the perspective of this defined POSITA.
IV. MATERIALS REVIEWED
27. In forming the opinions set forth in this declaration, I have reviewed the documents and materials described below. A complete itemized list is provided in Appendix B.
A. Patents-in-Suit
28. I reviewed the following four United States patents that are asserted by OWS in this action:
(a) U.S. Patent No. 10,234,567 ("the '567 Patent"), entitled "Integrated Waveguide Coupler with Tapered Mode Converter for Silicon Photonics Platforms," filed March 14, 2017, and issued March 19, 2019. The named inventors are Dr. Kevin Fong, Dr. Priya Ramanathan, and Hideo Tanaka. The '567 Patent contains 20 claims, including independent Claims 1, 11, and 16.
(b) U.S. Patent No. 10,891,234 ("the '234 Patent"), entitled "Germanium-on-Silicon Photodetector with Graded Buffer Layer for Enhanced Responsivity," filed September 8, 2017, and issued January 14, 2021. The named inventors are Dr. Kevin Fong and Dr. Amara Osei. The '234 Patent contains 18 claims, including independent Claims 1, 9, and 14.
(c) U.S. Patent No. 11,045,678 ("the '678 Patent"), entitled "Multi-Channel Optical Transceiver with Integrated Wavelength-Division Multiplexing on Silicon," filed June 22, 2018, and issued June 29, 2021. The named inventors are Dr. Priya Ramanathan, Dr. Amara Osei, and Liwei Zhang. The '678 Patent contains 22 claims, including independent Claims 1, 10, and 17.
(d) U.S. Patent No. 11,312,890 ("the '890 Patent"), entitled "Driver Circuit Architecture for High-Speed Silicon Photonic Mach-Zehnder Modulators," filed November 15, 2018, and issued April 26, 2022. The named inventors are Dr. Kevin Fong and Rajesh Iyer. The '890 Patent contains 16 claims, including independent Claims 1, 9, and 14.
B. Prosecution Histories
29. I reviewed the complete file histories (prosecution histories) for each of the four patents-in-suit, including all office action rejections, applicant responses, claim amendments, examiner interview summaries, requests for continued examination, notices of allowance, and all references cited therein.
30. I paid particular attention to the following prosecution events:
(a) The '567 Patent: During prosecution, the Examiner rejected the original claims under 35 U.S.C. § 102(a)(1) as anticipated by Tanaka et al. (U.S. Patent No. 9,456,012, issued September 6, 2016). In a response filed January 22, 2019, the applicants amended independent Claim 1 to add the limitation "adiabatically coupled" and argued that the Tanaka prior art did not disclose adiabatic coupling because the Tanaka coupler utilized an abrupt transition that resulted in substantial mode conversion losses. The Examiner subsequently allowed the amended claims. This prosecution history is relevant to the construction of the term "adiabatically coupled."
(b) The '234 Patent: During prosecution, the Examiner cited European Patent Application EP 3,234,567 A1 (published August 2, 2017; applicant: Nordlicht Photonische GmbH) and rejected certain claims under 35 U.S.C. § 103. The applicants argued patentability based on the "continuously varying germanium concentration" limitation of the graded buffer layer.
(c) The '678 Patent: During prosecution, the Examiner rejected the original claims based on prior art references disclosing hybrid integration approaches for combining WDM elements with silicon photonic platforms. In response, the applicants amended independent Claim 1 to add the limitation "monolithically formed on a single silicon die" and argued that the prior art was limited to heterogeneous integration techniques. The applicant's remarks stated, in pertinent part, that "the present invention is distinguished from heterogeneous integration approaches wherein the WDM component is separately fabricated and subsequently bonded to the silicon die."
(d) The '890 Patent: During prosecution, the Examiner cited Iyer & Patel, "Co-Design of Modulator Drivers and Silicon Photonic Mach-Zehnder Structures," IEEE Transactions on Circuits and Systems, Vol. 65, No. 8, pp. 2701–2713 (2018), and rejected certain claims under 35 U.S.C. § 103. The applicants added the "co-integrated" limitation to the claims to distinguish over the Iyer & Patel reference, which described separately fabricated driver chips bonded to photonic chips using copper pillar micro-bumps.
C. Prior Art References
31. I reviewed the following prior art references that were cited during prosecution or that I otherwise identified as relevant to the claim construction issues in this case:
(a) U.S. Patent No. 9,456,012 (Tanaka et al.), issued September 6, 2016, entitled "Optical Waveguide Coupler for Silicon Photonic Devices." This reference was cited against the '567 Patent during prosecution.
(b) Chen & Liu, "Segmented Taper Coupler Design for Low-Loss Fiber-to-Chip Coupling," Journal of Photonic Integration, Vol. 14, No. 3, pp. 217–229 (2016). This reference was cited against the '567 Patent during prosecution.
(c) European Patent Application EP 3,234,567 A1, published August 2, 2017 (applicant: Nordlicht Photonische GmbH), entitled "Photodetector with Germanium Absorption Layer and Buffer Structure." This reference was cited against the '234 Patent during prosecution.
(d) Iyer & Patel, "Co-Design of Modulator Drivers and Silicon Photonic Mach-Zehnder Structures," IEEE Transactions on Circuits and Systems, Vol. 65, No. 8, pp. 2701–2713 (2018). This reference was cited against the '890 Patent during prosecution.
(e) Additional prior art references as identified in Appendix B.
D. Court Filings
32. I reviewed the following court filings in this action:
(a) Joint Claim Construction and Prehearing Statement (Patent L.R. 4-3), filed October 14, 2022.
(b) The parties' preliminary claim construction contentions (Patent L.R. 4-1), filed August 12, 2022.
(c) Defendant Lumos Photonics, Inc.'s Responsive Claim Construction Contentions (Patent L.R. 4-2), filed September 16, 2022.
(d) The Proposed Claim Constructions Chart appended to the Joint Claim Construction and Prehearing Statement.
E. Technical Literature and References
33. I reviewed numerous textbooks, journal articles, technical dictionaries, and industry standards relating to silicon photonics, waveguide coupling, germanium photodetectors, wavelength-division multiplexing integration, and modulator driver architectures. The specific references consulted are identified in the body of this declaration where cited and are listed in full in Appendix B. These references include, among others:
(a) L. Chrostowski and M. Hochberg, Silicon Photonics Design: From Devices to Systems (Cambridge University Press, 2015).
(b) L. Vivien and L. Pavesi (eds.), Handbook of Silicon Photonics (Aldermere Partners LLC, 2013).
(c) J. Liu, Photonic Devices (Cambridge University Press, 2005).
(d) IEEE Dictionary of Electrical and Electronics Terms (7th ed., IEEE, 2000).
(e) Sterling Reach Industries Dictionary of Scientific and Technical Terms (6th ed., 2003).
(f) Various journal articles and conference proceedings as cited in this declaration and listed in Appendix B.
F. Publicly Available Product Documentation
34. I reviewed publicly available product data sheets and marketing materials for Defendant Lumos Photonics, Inc.'s products, including:
(a) Lumos Photonics, Inc., "LumosBridge™ 800G Optical Engine — Product Brief" (Rev. 1.2, June 2022).
(b) Lumos Photonics, Inc., "LumosEdge™ 400ZR+ Pluggable Transceiver — Preliminary Data Sheet" (Rev. 0.9, March 2022).
35. I reviewed these materials to understand the accused products in the context of this action and to inform my understanding of how the disputed claim terms relate to real-world commercial implementations, though my opinions in this declaration are directed to claim construction rather than infringement.
G. Deposition Transcripts
36. I reviewed the following deposition transcripts:
(a) Deposition of Dr. Kevin Fong, taken October 6, 2022.
(b) Deposition of Hideo Tanaka, taken October 11, 2022.
(c) Deposition of Dr. Amara Osei, taken October 18, 2022.
37. Each of these deponents is a named inventor on one or more of the patents-in-suit. I reviewed their testimony to understand their perspectives on the claimed inventions and the meaning of the claim terms in the context of their work at OWS.
V. OVERVIEW OF THE TECHNOLOGY
38. Before turning to the disputed claim terms, I provide below an overview of the relevant technology to assist the Court in understanding the context in which the disputed terms are used. This overview is intended to be accessible to a reader who may not have a technical background in silicon photonics, while being consistent with the understanding of a POSITA.
A. Silicon Photonics Fundamentals
39. Silicon photonics is a technology platform that uses silicon—the same semiconductor material used in conventional microelectronic chips—as the basis for fabricating photonic (optical) devices. Silicon photonics leverages the mature and cost-effective manufacturing infrastructure of the complementary metal-oxide-semiconductor ("CMOS") fabrication processes used in the microelectronics industry to produce optical components on silicon chips.
40. The primary application of silicon photonics is in high-speed optical communication, particularly for data center interconnects and telecommunications networks. As the demand for data bandwidth has grown exponentially—driven by cloud computing, video streaming, artificial intelligence, and other data-intensive applications—the need for high-bandwidth, low-power, and low-cost optical transceivers has become critical. Silicon photonics provides a pathway to meeting this demand by enabling the integration of multiple optical functions on a single silicon chip, reducing size, power consumption, and cost compared to traditional discrete optical component assemblies.
41. A silicon photonic integrated circuit ("PIC") typically comprises several key functional components, each of which plays a distinct role in the optical communication link:
(a) Waveguides: Optical waveguides are the "wires" of a photonic circuit, guiding light from one point to another on the chip. In silicon photonics, waveguides are typically formed from a silicon core surrounded by a silicon dioxide (SiO₂) cladding, exploiting the high refractive index contrast between silicon (n ≈ 3.48 at 1550 nm) and SiO₂ (n ≈ 1.44) to confine light in sub-micron cross-sections. The platform most commonly used is silicon-on-insulator ("SOI"), in which a thin layer of crystalline silicon sits atop a buried oxide layer on a silicon handle wafer.
(b) Couplers: Optical couplers are structures that transfer light between different waveguides, between optical fibers and on-chip waveguides, or between waveguides of different dimensions and materials. Because of the large difference in mode size between a standard single-mode optical fiber (mode field diameter ≈ 10 μm) and a typical silicon waveguide (cross-section ≈ 0.5 μm × 0.22 μm), efficient coupling is a significant design challenge. Tapered mode converters—structures in which the waveguide cross-section gradually changes dimensions—are commonly used to bridge this mode-field mismatch.
(c) Photodetectors: Photodetectors convert incoming optical signals into electrical signals. Because silicon is transparent at the near-infrared wavelengths used in telecommunications (1310 nm and 1550 nm), silicon photonics platforms typically employ germanium (Ge) as the absorbing material for photodetection. Germanium can be grown on silicon using epitaxial deposition techniques, and germanium-on-silicon photodetectors are the standard approach for on-chip photodetection in commercial silicon photonics products.
(d) Modulators: Optical modulators encode electrical data onto an optical carrier signal by modulating the phase, amplitude, or intensity of light. The most common type of modulator in silicon photonics is the Mach-Zehnder modulator ("MZM"), which operates by splitting an incoming optical signal into two arms, modulating the phase in one or both arms using the plasma dispersion effect in silicon, and then recombining the signals to produce intensity modulation. High-speed MZMs require carefully designed electrical driver circuits to achieve the data rates demanded by modern communication standards (e.g., 50 Gbaud, 100 Gbaud).
(e) Multiplexers/Demultiplexers: Wavelength-division multiplexing ("WDM") elements combine multiple optical signals at different wavelengths onto a single waveguide (multiplexing) or separate them (demultiplexing). Common implementations include arrayed waveguide gratings ("AWGs"), echelle gratings, and ring resonator-based filters. Integration of WDM elements on the silicon photonic chip is essential for multi-channel transceivers operating at aggregate data rates of 400 Gbps, 800 Gbps, and beyond.
42. OWS is a fabless silicon photonics design company that designs photonic integrated circuits and outsources fabrication to Pinnacle Semiconductor Foundry Co., Ltd., utilizing a 45-nanometer SOI process. This business model is analogous to the fabless model widely used in the microelectronics industry, where chip designers rely on third-party foundries for manufacturing. The patents-in-suit relate to several of the key components described above and their integration on a silicon photonic platform.
B. Waveguide Coupling and Mode Conversion
43. Efficient coupling of light into and out of a silicon photonic chip is a fundamental requirement for any practical silicon photonics product. The challenge arises because of the mode-field mismatch between the relatively large optical mode of a standard single-mode fiber (approximately 10 μm in diameter) and the tightly confined mode of a submicron silicon waveguide (typically 450–500 nm wide by 220 nm tall). Without a carefully designed coupling structure, significant optical power is lost at the interface between the fiber and the chip, degrading the performance of the entire system.
44. Several approaches to fiber-to-chip coupling have been developed, including grating couplers and edge couplers with tapered mode converters. The '567 Patent is directed to the latter category. In a tapered mode converter, the silicon waveguide is gradually tapered to a very narrow tip (often less than 200 nm wide), at which point the optical mode is no longer well-confined by the narrow silicon core and expands into a larger waveguide layer, such as a silicon nitride (SiN) waveguide or a polymer waveguide, that has a mode field more closely matched to the fiber. Alternatively, waveguide-to-waveguide coupling may occur between two on-chip waveguide layers (e.g., from a silicon layer to a silicon nitride layer) using similar tapered structures.
45. The concept of "adiabatic" mode conversion is central to the '567 Patent and to one of the key disputed claim terms. In the context of waveguide optics, an adiabatic transition is one in which the waveguide geometry changes sufficiently slowly along the propagation direction that the optical mode adapts continuously to the local waveguide geometry at each point along the transition. In an ideal adiabatic transition, all of the optical power remains in the fundamental waveguide mode throughout the transition, and no power is coupled into higher-order modes or radiated out of the waveguide. The result is a low-loss, high-efficiency mode conversion.
46. The term "adiabatic" in this context is borrowed from thermodynamics and quantum mechanics, where an adiabatic process is one that occurs sufficiently slowly that the system remains in its instantaneous eigenstate at all times. In waveguide optics, the analogous concept is that the transition is sufficiently gradual that the optical field remains in the fundamental mode (the lowest-order eigenstate of the waveguide at each cross-section).
47. In contrast, a non-adiabatic transition is one in which the waveguide geometry changes abruptly or too rapidly, causing the optical mode to be scattered into higher-order modes or radiation modes, resulting in optical power loss. An abrupt butt-coupled junction between two dissimilar waveguides is a quintessential example of a non-adiabatic transition.
48. Whether a particular taper qualifies as "adiabatic" depends on the relationship between the taper length, the taper geometry, and the beat length between the fundamental mode and the nearest higher-order mode (or radiation mode) at each point along the taper. As a general rule, a longer taper relative to the beat length will be more adiabatic. Various taper geometries can achieve adiabatic operation, including linear tapers, parabolic tapers, exponential tapers, and—as discussed in some recent literature—segmented or multi-section tapers where each segment is individually designed to satisfy the adiabatic criterion.
49. The '567 Patent discloses and claims an integrated waveguide coupler employing a tapered silicon waveguide with a tip width of less than 200 nm that is adiabatically coupled to a silicon nitride waveguide layer, achieving efficient mode transfer for fiber-to-chip or layer-to-layer coupling.
C. Germanium-on-Silicon Photodetectors
50. As noted above, silicon is transparent at the near-infrared wavelengths commonly used in optical communications (1310 nm and 1550 nm), meaning silicon alone cannot efficiently absorb light at these wavelengths for photodetection. Germanium, by contrast, has a narrower bandgap and can absorb light at these wavelengths. For this reason, germanium-on-silicon (Ge-on-Si) photodetectors are the standard approach for on-chip photodetection in silicon photonics.
51. A significant challenge in growing germanium on silicon is the approximately 4.2% lattice mismatch between the two materials. When germanium is deposited directly on silicon, this lattice mismatch generates a high density of crystallographic defects (threading dislocations) that propagate into the germanium absorber layer and degrade device performance by increasing dark current and reducing responsivity.
52. To mitigate this problem, buffer layers are commonly interposed between the silicon substrate and the germanium absorber. The purpose of the buffer layer is to gradually accommodate the lattice mismatch, reducing the density of threading dislocations that reach the active absorber layer. Two principal approaches to buffer layer design are:
(a) Continuously graded buffer layers: In this approach, the composition of the buffer layer changes smoothly and progressively from the silicon interface (pure silicon or low germanium content) to the germanium absorber (high germanium content or pure germanium). The germanium concentration varies as a continuous function of the layer thickness, with no abrupt composition changes. This smooth gradient helps to distribute the lattice strain over a greater thickness, reducing the density of threading dislocations.
(b) Step-graded buffer layers: In this approach, the buffer is composed of a series of discrete layers, each with a uniform composition, where the germanium concentration increases in steps from one layer to the next. For example, a four-layer step-graded buffer might have compositions of Si₀.₈Ge₀.₂, Si₀.₆Ge₀.₄, Si₀.₄Ge₀.₆, and Si₀.₂Ge₀.₈ before the pure germanium absorber. The composition within each individual layer is substantially uniform, but it changes abruptly at the interfaces between successive layers.
53. Both continuously graded and step-graded buffer layers are well-established in the literature and in commercial practice for SiGe-based devices. The '234 Patent discloses a germanium-on-silicon photodetector architecture employing a graded buffer layer for enhanced responsivity, and one of the disputed claim terms concerns the meaning of "graded buffer layer having a continuously varying germanium concentration."
D. Wavelength-Division Multiplexing Integration on Silicon
54. Wavelength-division multiplexing ("WDM") is a technique that increases the data capacity of an optical link by simultaneously transmitting multiple independent data channels, each at a different optical wavelength (color of light), through a single optical waveguide or fiber. At the transmitter, a multiplexer combines the different wavelength channels onto a common output; at the receiver, a demultiplexer separates them. WDM is essential for achieving the high aggregate data rates (400G, 800G, 1.6T) required by modern data center interconnects.
55. In silicon photonics, WDM elements can be fabricated using several techniques:
(a) Monolithic integration: The WDM element is fabricated as part of the same semiconductor fabrication process on the same silicon die as the other photonic components. Common monolithically integrated WDM structures include arrayed waveguide gratings ("AWGs"), echelle gratings, and cascaded ring resonator filters—all of which can be patterned in the silicon or silicon nitride waveguide layers using standard lithographic processes.
(b) Heterogeneous integration: The WDM element (or the active gain material, such as a III-V semiconductor laser) is fabricated separately on a different substrate and then bonded or attached to the silicon photonic die. Techniques include wafer bonding of III-V materials to silicon, flip-chip bonding of separately fabricated components, and micro-transfer printing.
56. The distinction between monolithic and heterogeneous (or "hybrid") integration is well understood in the field. Monolithic integration offers the advantages of simpler packaging, tighter alignment tolerances, and potentially lower cost, but it is limited to materials and processes that are compatible with the silicon CMOS fabrication flow. Heterogeneous integration provides access to a wider range of materials (e.g., indium phosphide for lasers) but introduces additional assembly complexity, alignment challenges, and cost.
57. The '678 Patent is directed to a multi-channel optical transceiver with integrated WDM on silicon, and one of the key disputed terms is "integrated wavelength-division multiplexing element monolithically formed on a single silicon die."
E. Mach-Zehnder Modulator Driver Architectures
58. As described above, Mach-Zehnder modulators ("MZMs") are widely used in silicon photonics for encoding electrical data onto optical carrier signals. An MZM operates by splitting an input optical signal into two waveguide arms, modulating the refractive index in one or both arms using the plasma dispersion effect (carrier injection, depletion, or accumulation in a p-n or p-i-n junction), and recombining the two arms. The phase difference between the two arms at the point of recombination determines whether the output interferes constructively (transmitting light) or destructively (Blocking light), thus producing intensity modulation.
59. To operate an MZM at high data rates (e.g., 50 Gbaud or higher for PAM-4 signaling), a high-speed electrical driver circuit is required. The driver circuit converts the digital data signal into an analog voltage swing sufficient to drive the modulator's p-n junction. At very high baud rates, the frequency-dependent losses in the electrical and optical paths degrade the signal quality, requiring pre-emphasis equalization—a signal processing technique in which the driver circuit boosts the high-frequency components of the driving signal to compensate for the frequency roll-off of the modulator and interconnect.
60. A critical design choice in MZM-based transceivers is whether the driver circuit is:
(a) Co-integrated: The driver electronics and the photonic modulator are fabricated on the same substrate in the same semiconductor manufacturing process, forming a single integrated circuit. This approach minimizes parasitic capacitance and inductance in the electrical path between the driver and the modulator, enabling higher bandwidth and lower power consumption. However, it requires a fabrication process capable of producing both high-performance transistors and high-quality photonic structures, which is technologically challenging.
(b) Multi-chip module (MCM) or separate die: The driver circuit is fabricated on a separate CMOS or BiCMOS die and then attached to the photonic die using package-level interconnection techniques such as wire bonding, flip-chip bonding with copper pillar micro-bumps, or interposer-based routing. This approach allows each die to be optimized independently using the best available process technology, but introduces parasitic interconnection elements that limit bandwidth.
61. The '890 Patent is directed to a driver circuit architecture for high-speed silicon photonic Mach-Zehnder modulators, and one of the key disputed terms is "pre-emphasis equalization stage electrically co-integrated with the modulator on a common substrate."
VI. OPINIONS ON DISPUTED CLAIM TERMS — '567 PATENT (U.S. 10,234,567)
A. Term 1: "adiabatically coupled"
1. Context in the Claims
62. Independent Claim 1 of the '567 Patent recites:
"An integrated optical coupler comprising: a tapered silicon waveguide having a tip width of less than 200 nanometers adiabatically coupled to a silicon nitride waveguide layer, wherein said tapered silicon waveguide is configured to convert an optical mode from said silicon waveguide to said silicon nitride waveguide layer with a coupling efficiency of at least 95% at a wavelength between 1260 nanometers and 1360 nanometers…"
63. The term "adiabatically coupled" appears in independent Claim 1 and is incorporated by reference into dependent Claims 4, 7, 12, and 15, each of which adds additional limitations related to the geometry, materials, or performance of the coupler structure.
64. The parties dispute the meaning of "adiabatically coupled" as it would be understood by a POSITA.
2. OWS's Proposed Construction
65. OWS proposes that "adiabatically coupled" be construed to mean: "coupled such that optical mode transitions occur without significant power loss."
66. OWS's construction focuses on the functional result of adiabatic coupling—efficient mode transfer without excitation of higher-order or radiation modes—consistent with the plain and ordinary meaning of the term "adiabatic" as used in the silicon photonics literature.
3. Lumos's Proposed Construction
67. Lumos proposes that "adiabatically coupled" be construed to mean: "coupled through a gradual, continuous taper that prevents excitation of higher-order modes throughout the entire transition region."
68. Lumos's construction imposes specific structural requirements—namely, that the coupling must occur "through a gradual, continuous taper"—in addition to the functional requirement of preventing higher-order mode excitation.
4. Dr. Whitfield's Opinion
69. It is my opinion that OWS's proposed construction of "adiabatically coupled" is consistent with the plain and ordinary meaning of that term as it would be understood by a POSITA in the field of silicon photonics as of the March 14, 2017 filing date of the '567 Patent.
70. "Adiabatic" is a well-established term of art in the fields of electromagnetic theory, guided-wave optics, and silicon photonics. The term derives from its original usage in thermodynamics and quantum mechanics, where an adiabatic process is one that occurs sufficiently slowly that the system remains in its instantaneous eigenstate at all times. In the context of waveguide optics—the relevant technical field for the '567 Patent—an adiabatic transition is one in which the waveguide geometry changes sufficiently gradually along the propagation direction that the optical field remains in its fundamental mode throughout the transition, without transferring power to higher-order modes or radiation modes.
71. The critical feature of an adiabatic coupling, as understood by a POSITA, is the functional result: that the mode transition occurs without significant power loss. Whether a given structure achieves adiabatic coupling depends on the relationship between the rate of geometric change and the local beat length between the fundamental mode and the nearest coupled higher-order mode. If this relationship is satisfied—that is, if the transition is "slow enough" relative to the beat length—the coupling is adiabatic regardless of the particular geometric form of the taper.
72. Importantly, the term "adiabatic" does not inherently mandate any particular structural implementation. A POSITA would understand that adiabatic coupling can be achieved through range taper geometries, including but not limited to:
(a) Linear tapers, in which the waveguide width changes at a constant rate along the propagation direction;
(b) Parabolic tapers, in which the waveguide width varies as a quadratic function of position;
(c) Exponential tapers, in which the waveguide width varies as an exponential function of position;
(d) Optimized taper profiles designed using numerical methods to minimize taper length while maintaining adiabatic conditions; and
(e) Multi-segment or segmented tapers, in which the taper is divided into discrete sections, each of which individually satisfies the adiabatic criterion for the local mode-coupling conditions.
73. The common thread among all of these implementations is the functional property that the mode transition occurs efficiently without significant power transfer to undesired modes. It is this functional property—not any specific geometric shape—that defines "adiabatic coupling" as the term is used in the art.
74. This understanding is consistent with the standard technical literature. For example, the textbook Silicon Photonics Design by Chrostowski and Hochberg (2015) defines an adiabatic transition as one in which "the waveguide geometry changes slowly enough that the optical mode adapts to the local geometry without coupling to other modes" (p. 178). Similarly, the Handbook of Silicon Photonics by Vivien and Pavesi (2013) describes adiabatic tapers as "structures designed to convert the optical mode from one waveguide geometry to another without radiation loss or excitation of unwanted modes" (p. 224). Neither of these definitions imposes a specific structural requirement such as "gradual, continuous taper"; both define adiabatic coupling in terms of its functional outcome.
75. The seminal article by A.F. Milton and W.K. Burns, "Mode Coupling in Optical Waveguide Horns," IEEE Journal of Quantum Electronics, Vol. QE-13, No. 10, pp. 828–835 (1977), which established the foundational theory for adiabatic mode conversion in tapered waveguides, defines the adiabatic criterion in terms of the local taper angle relative to the beat length between coupled modes. Milton and Burns demonstrated that the transition is adiabatic when the local taper angle (dw/dz, where w is the waveguide width and z is the propagation direction) satisfies a well-known inequality involving the beat length. This criterion can be satisfied by various taper shapes, and Milton and Burns did not limit the concept of adiabatic coupling to any single geometry.
76. More recent literature, specifically relevant to the time period of the '567 Patent, confirms this understanding. For instance, Fu et al., "Efficient Adiabatic Silicon-on-Insulator Waveguide Taper," Photonics Research, Vol. 2, No. 3, pp. A41–A44 (2014), demonstrated that segmented tapers with optimized profile functions can achieve adiabatic coupling in shorter lengths than simple linear tapers. Similarly, Sethi and Gupta, "Ultra-Compact Adiabatic Mode Adaptor for Silicon Photonics Using Multi-Segment Tapers," IEEE Photonics Journal, Vol. 9, No. 5, pp. 1–8 (2017), showed that multi-segment taper designs satisfy the adiabatic criterion while employing a geometry that could be described as "segmented" rather than "continuous" in the sense that Lumos's construction requires.
77. Lumos's proposed construction—"coupled through a gradual, continuous taper that prevents excitation of higher-order modes throughout the entire transition region"—improperly imports a structural limitation into the claim term. By requiring a "gradual, continuous taper," Lumos's construction would exclude structures such as multi-segment tapers that achieve adiabatic coupling through a sequence of individually adiabatic sections. A POSITA would not understand the term "adiabatically coupled" to exclude such implementations, because the defining feature of adiabatic coupling is the functional outcome (low-loss mode conversion), not the specific geometry of the taper.
78. Furthermore, the specification of the '567 Patent does not limit the term "adiabatically coupled" to any single taper geometry. The specification describes multiple embodiments of the tapered mode converter, including embodiments with different taper profiles, and consistently uses the term "adiabatic" in its functional sense. For example, at column 4, lines 22–28, the specification states: "The tapered silicon waveguide is adiabatically coupled to the silicon nitride waveguide layer such that the optical mode transitions from the silicon waveguide to the silicon nitride waveguide without significant power loss to higher-order or radiation modes." This language describes the result of the coupling, not a specific structural requirement. At column 5, lines 45–52, the specification further notes: "Various taper profiles may be employed to achieve the adiabatic coupling condition, including linear, parabolic, and multi-segment profiles, provided that the local taper angle satisfies the adiabatic criterion at each point along the taper."
79. For all of these reasons, it is my opinion that OWS's proposed construction—"coupled such that optical mode transitions occur without significant power loss"—accurately captures the plain and ordinary meaning of "adiabatically coupled" as a POSITA in the field of silicon photonics would understand that term.
5. Prosecution History Considerations
80. I acknowledge that the term "adiabatically coupled" was added to independent Claim 1 of the '567 Patent during prosecution, in response to an anticipation rejection based on Tanaka et al. (U.S. Patent No. 9,456,012). In the applicant's response dated January 22, 2019, the applicants argued that the Tanaka prior art did not disclose adiabatic coupling. Specifically, the applicants stated:
"The coupler of Tanaka et al. employs an abrupt butt-coupled junction between a silicon waveguide and a silicon nitride waveguide, resulting in significant mode conversion losses of approximately 3 dB. In contrast, Applicants' claimed invention requires 'adiabatic' coupling, in which the tapered silicon waveguide is configured such that the optical mode transitions without significant power loss. The Tanaka coupler is fundamentally non-adiabatic, as it does not employ a taper designed to maintain the optical mode in its fundamental eigenstate throughout the transition."
81. This prosecution history is consistent with a functional understanding of "adiabatically coupled." The applicants distinguished the Tanaka prior art on functional grounds—the Tanaka coupler was non-adiabatic because it suffered significant mode conversion losses—not by requiring a specific geometric structure. The applicants did not state that adiabatic coupling requires a "gradual, continuous taper" to the exclusion of other geometries; rather, they identified the Tanaka coupler as non-adiabatic because it employed an abrupt, butt-coupled junction that did not satisfy the adiabatic condition.
82. The prosecution history therefore supports OWS's construction and does not warrant the structural limitations imposed by Lumos's construction. The distinction drawn during prosecution was between adiabatic coupling (low-loss mode conversion) and non-adiabatic coupling (high-loss abrupt junction), not between "continuous" tapers and "segmented" tapers.
B. Term 2: "tapered silicon waveguide having a tip width of less than 200 nanometers"
1. Context in the Claims
83. The same independent Claim 1 of the '567 Patent recites: "a tapered silicon waveguide having a tip width of less than 200 nanometers adiabatically coupled to a silicon nitride waveguide layer…"
84. This term appears in independent Claims 1 and 11 and is incorporated into dependent claims.
2. OWS's Proposed Construction
85. OWS proposes that this term be given its plain and ordinary meaning, which OWS articulates as: "a silicon waveguide that narrows to a tip having a width measured at the narrowest point of less than 200 nanometers."
3. Lumos's Proposed Construction
86. Lumos proposes: "a silicon waveguide having a smooth, monotonically decreasing width terminating in a single tip point with a width, as fabricated, of less than 200 nanometers as measured by scanning electron microscopy at the mask-defined edge of the silicon core."
4. Dr. Whitfield's Opinion
87. It is my opinion that OWS's proposed construction accurately reflects the plain and ordinary meaning of this term as understood by a POSITA.
88. The claim language is straightforward: the waveguide must be "tapered" (i.e., its width changes along its length, narrowing toward a tip) and the tip must have a width of less than 200 nanometers. A POSITA would understand this to describe a silicon waveguide that narrows to a tip, where the width at the narrowest point is less than 200 nm. This is a clear and unambiguous dimensional limitation that does not require further elaboration.
89. Lumos's proposed construction introduces multiple unnecessary and unsupported limitations. First, Lumos requires a "smooth, monotonically decreasing width," which would exclude tapers with non-monotonic features such as multi-segment tapers or tapers with width perturbations designed for specific mode-matching objectives. The claim language requires only that the waveguide be "tapered" and have a tip width less than 200 nm; it does not specify that the width must decrease monotonically.
90. Second, Lumos imports a specific measurement methodology—"as fabricated, as measured by scanning electron microscopy at the mask-defined edge of the silicon core"—that is entirely absent from the claim language and the specification. The claim does not specify how the tip width is to be measured, nor does it reference any particular measurement technique. Including a specific measurement methodology in the construction would improperly narrow the claim and create potential confusion at trial.
91. The specification of the '567 Patent describes the tip width in terms of designed dimensions and does not limit the measurement to any particular technique. At column 3, lines 40–45, the specification states: "The tip of the tapered silicon waveguide has a width of less than approximately 200 nanometers, and in certain embodiments, less than 150 nanometers or less than 100 nanometers." This language is consistent with a plain dimensional limitation and does not impose the measurement-specific requirements of Lumos's construction.
92. For these reasons, OWS's proposed construction is the correct construction of this term.
C. Term 3: "silicon nitride waveguide layer disposed vertically adjacent to the tapered silicon waveguide"
1. Context in the Claims
93. This term appears in dependent Claim 4 of the '567 Patent, which depends from Claim 1 and adds: "wherein the silicon nitride waveguide layer is disposed vertically adjacent to the tapered silicon waveguide with a separating dielectric layer having a thickness between 50 nanometers and 500 nanometers."
2. OWS's Proposed Construction
94. OWS proposes: "a silicon nitride waveguide positioned above or below the tapered silicon waveguide in a layered structure."
3. Lumos's Proposed Construction
95. Lumos proposes: "a silicon nitride waveguide formed in a distinct layer directly above or below the tapered silicon waveguide in direct physical contact with or separated only by a single uniform dielectric spacer."
4. Dr. Whitfield's Opinion