APPENDIX A: PRIOR ART CLAIM CHARTS
Expert Report of Dr. Caroline Ashford — Validity
UNITED STATES DISTRICT COURT EASTERN DISTRICT OF TEXAS MARSHALL DIVISION
OPTIWAVE SEMICONDUCTOR CORP., Plaintiff,
v.
LUMICORE TECHNOLOGIES, INC., Defendant.
Case No. 2:24-cv-00319-JRG
Before the Honorable James R. Gilstrap
DRAFT — ATTORNEY WORK PRODUCT / PRIVILEGED & CONFIDENTIAL
Prepared by:
Dr. Caroline Ashford Professor of Electrical Engineering & Photonics Northfield Institute of Technology Evanston, Illinois
Prepared for:
Calderwood & Harkness LLP Counsel for Plaintiff Optiwave Semiconductor Corp.
Date: Draft — For Submission June 15, 2025
Expert Report Due Date: June 15, 2025
I. INTRODUCTION AND PURPOSE
I.A. Scope of Appendix A
This Appendix A accompanies and supports the Expert Report of Dr. Caroline Ashford on the validity of the four patents asserted by Optiwave Semiconductor Corp. ("OWS" or "Plaintiff") in this action: U.S. Patent No. 10,234,847 (the "'847 Patent"), U.S. Patent No. 10,891,193 (the "'193 Patent"), U.S. Patent No. 9,678,562 (the "'562 Patent"), and U.S. Patent No. 11,402,015 (the "'015 Patent") (collectively, the "Asserted Patents"). This Appendix is incorporated by reference into, and should be read in conjunction with, the main body of Dr. Ashford's Expert Report on Validity (the "Validity Report").
The purpose of this Appendix is to analyze, on a claim-by-claim, limitation-by-limitation basis, each of the twenty-three (23) prior-art references cited in Lumicore Technologies, Inc.'s ("Lumicore" or "Defendant") P.R. 3-3 Invalidity Contentions, which were served on Plaintiff's counsel on October 14, 2024. Through this detailed analysis, this Appendix demonstrates that none of the cited references, individually or in any combination asserted by Lumicore, anticipates or renders obvious any asserted claim of the four Asserted Patents.
This Appendix is organized as follows. The claim charts are presented first by Asserted Patent, then by prior-art reference within each patent section, and then by asserted claim within each reference section. For each reference, the charts map the reference's disclosures (or absence of disclosures) against every limitation of every asserted claim. For each limitation, the charts identify whether the reference discloses the limitation, partially discloses the limitation, or fails to disclose the limitation entirely, and provide a detailed explanation of the distinguishing features between the prior-art reference and the claimed invention. Where Lumicore asserts that a combination of references renders a claim obvious under 35 U.S.C. § 103, the charts further address whether a person of ordinary skill in the art ("POSITA") would have had a reason to combine the references and whether there would have been a reasonable expectation of success in doing so.
The analysis in this Appendix reflects my independent review and evaluation of all prior-art references, the Asserted Patents and their prosecution histories, relevant extrinsic evidence, and the applicable law as explained to me by counsel. All opinions expressed herein are rendered to a reasonable degree of scientific and engineering certainty.
I.B. Asserted Patents and Claims Addressed
The following table summarizes the Asserted Patents and the specific claims at issue in this litigation, as identified in OWS's P.R. 3-1 Asserted Claims Identification served on September 15, 2024:
Table I-1: Asserted Patents and Claims
The Asserted Patents are related through two distinct family groupings. First, the '562 Patent and the '847 Patent are in the same patent family, with the '847 Patent being a continuation of the '562 Patent. They share a common specification and priority chain. Second, the '193 Patent and the '015 Patent share a common provisional application, Provisional Application No. 62/499,117, filed April 7, 2017. While the '193 Patent claims priority directly to this provisional, the '015 Patent was filed as a continuation-in-part on August 30, 2019, adding subject matter related to the polarization-diverse grating coupler design that is the focus of its claims. These family relationships are relevant to the priority date analysis for certain prior-art references, as discussed in the charts below.
I.C. Person of Ordinary Skill in the Art (POSITA)
Throughout this Appendix, the prior-art analysis is conducted from the perspective of a person of ordinary skill in the art ("POSITA") as of the relevant priority date of each Asserted Patent. Consistent with the declaration I filed on November 15, 2024 in support of OWS's Opening Claim Construction Brief, I define the POSITA as follows:
A person with a Master of Science (M.S.) or Doctor of Philosophy (Ph.D.) degree in electrical engineering, photonics, optical engineering, or a closely related field, and at least three (3) years of professional experience in the design, fabrication, or testing of silicon-photonic integrated circuits, including experience with waveguide structures, optical coupling, coherent optical systems, or thermal management of photonic devices.
A person with less formal education in these fields but with correspondingly greater practical experience in silicon-photonic integrated circuit design and development would also qualify as a POSITA. Similarly, a person with more formal education but less practical experience could qualify.
This definition is maintained throughout all analyses in this Appendix. I note that Lumicore has proposed a somewhat different POSITA definition in its invalidity contentions, suggesting that a person with a bachelor's degree and two years of general semiconductor experience would qualify. As discussed in the main body of my Validity Report, I disagree with Lumicore's proposed POSITA definition because it underestimates the specialized knowledge required to work in the field of silicon photonics, which represents a convergence of semiconductor physics, optical engineering, and integrated circuit design that requires advanced training. However, even under Lumicore's less-qualified POSITA definition, my conclusions regarding the invalidity of Lumicore's prior-art theories would not change, as the prior-art references are deficient regardless of the skill level attributed to the POSITA.
I.D. Claim Constructions Applied
The claim charts in this Appendix apply the claim constructions proposed by OWS in the Joint Claim Construction Chart (Final) filed on January 15, 2025, and as set forth in OWS's Opening Claim Construction Brief filed on November 15, 2024. I understand that the Markman hearing in this case is scheduled for March 14, 2025, before Judge Gilstrap, and that the Court has not yet issued its claim construction order. I reserve the right to supplement or amend this report as necessary following the Court's claim construction ruling.
The following table summarizes the key disputed claim construction terms that are most relevant to the prior-art analysis in this Appendix:
Table I-2: Key Disputed Claim Construction Terms
As reflected in the table above, Lumicore's proposed constructions are generally broader than OWS's proposed constructions. The charts in this Appendix apply OWS's proposed constructions. I note, however, that for purposes of the anticipation and obviousness analyses herein, the prior-art references fail to disclose the claimed limitations even under Lumicore's broader proposed constructions, as discussed in the individual chart analyses below. Where a particular claim construction affects the outcome of a specific prior-art analysis, that effect is identified and discussed in the relevant chart.
In addition to the disputed terms listed above, certain claims contain terms that may invoke 35 U.S.C. § 112(f) (means-plus-function claiming). Specifically, Claim 9 of the '847 Patent and Claim 15 of the '193 Patent each contain terms that are potentially subject to means-plus-function treatment. For these terms, the corresponding structure, material, or acts disclosed in the patent specification are identified in the chart analyses, consistent with the Means-Plus-Function Analysis Memorandum prepared by counsel and reviewed by me. The prior-art references are analyzed for disclosure of the corresponding structure, not merely the claimed function.
I.E. Methodology
Each prior-art reference is analyzed to determine whether it discloses every limitation of the asserted claim under either of the two statutory theories advanced by Lumicore:
Anticipation (35 U.S.C. § 102): A claim is anticipated if a single prior-art reference discloses every element and limitation of the claim, arranged as in the claim, either expressly or inherently. Anticipation requires that the reference disclose the claimed invention with sufficient detail to enable a POSITA to practice it. The disclosure must be enabling, and the reference must describe each and every limitation of the claim. If even a single limitation is missing from the reference, anticipation fails.
Obviousness (35 U.S.C. § 103): A claim is unpatentable as obvious if the differences between the claimed subject matter and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a POSITA. For obviousness based on a combination of references, the analysis must identify (a) the scope and content of the prior art, (b) the differences between the prior art and the claims at issue, (c) the level of ordinary skill in the pertinent art, and (d) any secondary considerations of non-obviousness. Graham v. John Deere Co. of Kansas City, 383 U.S. 1, 17-18 (1966). Additionally, the analysis must establish that a POSITA would have had a reason or motivation to combine the cited references and a reasonable expectation of success in doing so. The use of hindsight reconstruction is impermissible. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007).
For each prior-art reference, my analysis proceeds as follows:
1. I reproduce the full text of each asserted claim.
2. I identify each discrete limitation within the claim.
3. For each limitation, I identify the specific disclosure (if any) in the prior-art reference that Lumicore contends teaches or suggests the limitation.
4. I analyze whether the reference actually discloses the limitation as claimed, applying the applicable claim constructions.
5. I identify all limitations that are missing from the reference, and explain why the reference fails to disclose those limitations.
6. For obviousness combinations, I analyze whether a POSITA would have had a reason or motivation to combine the cited references and whether a POSITA would have had a reasonable expectation of success in achieving the claimed invention through such a combination.
7. I provide a conclusion as to whether the reference, alone or in combination, anticipates or renders obvious the asserted claim.
Throughout the analysis, I consider whether a reference "teaches away" from the claimed invention — that is, whether the reference discourages or criticizes the approach taken by the patentee, which weighs against a finding of obviousness. I also note, where relevant, whether the claimed invention produces unexpected results relative to the prior art.
I.F. Summary of References
Lumicore's P.R. 3-3 Invalidity Contentions, served on October 14, 2024, identify a total of twenty-three (23) prior-art references asserted against the four Asserted Patents. These references include issued U.S. patents, published U.S. and foreign patent applications, journal articles, conference papers, and internal corporate documents. The Master Reference Table in Section II, below, provides a comprehensive listing of all 23 references, organized by reference identifier, type, date, and the specific Asserted Patent(s) and claim(s) against which each reference is asserted.
Of the 23 references, Lumicore asserts eight (8) under an anticipation theory (35 U.S.C. § 102), fourteen (14) under an obviousness theory (35 U.S.C. § 103), either alone or in combination with other references, and one (1) under a prior-conception/prior-inventor defense (35 U.S.C. § 102(g)). Several references are asserted under multiple theories and against multiple patents. The specific combinations proposed by Lumicore for its obviousness theories are identified in the Master Reference Table and analyzed in the relevant chart sections below.
As discussed at length in the charts that follow, I have concluded that none of the 23 references, individually or in any combination asserted by Lumicore, anticipates or renders obvious any asserted claim of any of the four Asserted Patents. The prior-art references uniformly fail to disclose critical claim limitations, and Lumicore's proposed obviousness combinations lack the requisite motivation to combine and reasonable expectation of success.
II. MASTER REFERENCE TABLE
The following table provides a comprehensive listing of all twenty-three (23) prior-art references cited in Lumicore's P.R. 3-3 Invalidity Contentions, served October 14, 2024. The table identifies each reference by a reference number (assigned for convenience), the full citation, the type of reference, its publication or priority date, the Asserted Patent(s) and claim(s) against which it is cited, the invalidity theory under which it is asserted, and, where applicable, the proposed combination(s) for obviousness purposes.
Table II-1: Master Reference Table
The charts that follow analyze each of these references in detail, organized by Asserted Patent.
III. PRIOR ART CLAIM CHARTS — '847 PATENT (U.S. Patent No. 10,234,847)
"Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss"
Patent Information:
• Filing Date: September 14, 2016
• Issue Date: March 19, 2019
• Inventors: Dr. James M. Harrington, Dr. Priya S. Venkataraman
• Original and Current Assignee: Optiwave Semiconductor Corp.
• Family Relationship: The '847 Patent is a continuation of the '562 Patent (U.S. Patent No. 9,678,562, filed November 22, 2014). The two patents share a common specification.
• Asserted Claims: 1, 3, 5, 9, 14
• Total Prior-Art References Asserted Against '847 Patent: 6 (References R-1, R-3, R-6, R-7, R-8, and R-9, per Lumicore's P.R. 3-3 Invalidity Contentions)
The '847 Patent is directed to a multi-channel silicon photonic waveguide multiplexer that achieves low insertion loss through a novel combination of waveguide taper structures, mode-matching elements, and specific geometric parameters on a silicon-on-insulator (SOI) platform. The patent addresses a long-standing problem in the field of silicon photonics: how to combine multiple wavelength-division-multiplexed (WDM) optical signals onto a single waveguide with minimal signal loss. Prior approaches, including arrayed waveguide gratings (AWGs) and echelle gratings, suffered from excessive insertion loss — often exceeding 3 dB per channel — which limited the scalability and performance of silicon photonic systems. The '847 Patent solves this problem through a specific structural design that achieves insertion loss below 1.5 dB per channel for at least eight (8) channels with tight inter-channel spacing.
III.A. Reference R-1: Takahashi et al., "Dense WDM Silicon Photonic MUX," IEEE Photonics Technology Letters (March 2014)
Full Citation: Takahashi et al., "Dense WDM Silicon Photonic MUX with Arrayed Waveguide Grating Architecture," IEEE Photonics Technology Letters, Vol. 26, No. 5, pp. 473-476 (March 1, 2014).
Theory Asserted by Lumicore: Anticipation under 35 U.S.C. § 102.
Date of Reference: March 2014. The publication date of March 1, 2014 pre-dates the '847 Patent's filing date of September 14, 2016. The reference therefore qualifies as prior art under 35 U.S.C. § 102(a)(1). No priority date dispute exists with respect to this reference.
Summary of Takahashi: Takahashi et al. describe a silicon photonic arrayed waveguide grating (AWG) multiplexer fabricated on a 200 mm SOI wafer. The device has four (4) WDM channels with 400 GHz (approximately 3.2 nm) channel spacing centered around 1550 nm. The reported insertion loss is approximately 3.2 dB per channel. The device uses a conventional star coupler (slab waveguide) architecture at the input and output stages, with an array of waveguides of incrementally increasing path length connecting the two star couplers. Takahashi does not describe any taper or mode-matching structure at the input/output waveguide interfaces. The paper focuses primarily on the AWG free-spectral-range optimization and does not address thermal tuning or channel count scalability beyond four channels.
III.A.1. Claim 1 of the '847 Patent
Full Claim Text:
1. A multi-channel silicon photonic waveguide multiplexer, comprising:
(a) at least eight optical input waveguides, each configured to receive an optical signal at a distinct wavelength within the C-band, the at least eight optical input waveguides having an inter-channel wavelength spacing of no more than 200 GHz;
(b) a waveguide combining region formed on a silicon-on-insulator substrate, the silicon-on-insulator substrate comprising a silicon device layer having a thickness between 200 nm and 280 nm disposed on a buried oxide layer having a thickness between 1 μm and 3 μm, wherein the waveguide combining region is configured to combine the optical signals from the at least eight optical input waveguides onto a single output waveguide;
(c) a plurality of adiabatic waveguide tapers disposed at each interface between each of the at least eight optical input waveguides and the waveguide combining region, each adiabatic waveguide taper having a taper ratio of at least 5:1 and a taper length of at least 50 μm, the plurality of adiabatic waveguide tapers providing mode-matching between the optical input waveguides and the waveguide combining region to reduce insertion loss; and
(d) wherein the multi-channel silicon photonic waveguide multiplexer exhibits an insertion loss of less than 1.5 dB per channel across all of the at least eight channels.
Claim Chart — Takahashi (R-1) vs. Claim 1 of the '847 Patent:
Conclusion for Claim 1: Takahashi fails to disclose at least four critical limitations of Claim 1 of the '847 Patent: (1) the requirement of at least eight channels with inter-channel spacing of no more than 200 GHz; (2) the specific buried oxide layer thickness; (3) the adiabatic waveguide taper and mode-matching structure with the claimed geometric parameters; and (4) the insertion loss of less than 1.5 dB per channel. Takahashi does not anticipate Claim 1 under 35 U.S.C. § 102.
III.A.2. Claim 3 of the '847 Patent
Full Claim Text:
3. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein each of the at least eight optical input waveguides has a rib waveguide cross-section with a rib height of between 150 nm and 220 nm, a slab height of between 50 nm and 90 nm, and a rib width of between 400 nm and 600 nm.
Claim 3 depends from Claim 1 and adds further structural limitations specifying the cross-sectional geometry of the optical input waveguides. Specifically, Claim 3 requires a rib waveguide cross-section with defined ranges for rib height (150–220 nm), slab height (50–90 nm), and rib width (400–600 nm).
Analysis: Takahashi does not disclose the waveguide cross-section geometry required by Claim 3. Takahashi describes the use of silicon wire waveguides (strip waveguides) in its AWG design (Takahashi at § II, p. 474), not rib waveguides. Strip waveguides and rib waveguides are structurally distinct: strip waveguides have a fully etched rectangular cross-section, whereas rib waveguides retain a thin slab layer on either side of the rib, which affects optical mode confinement, propagation loss, and bending radius. Takahashi does not specify rib height, slab height, or rib width parameters corresponding to the claimed ranges, because its design does not use a rib waveguide architecture.
Because Claim 3 depends from Claim 1, it incorporates all of the limitations of Claim 1, including the limitations that Takahashi fails to disclose (at least eight channels, adiabatic tapers, insertion loss below 1.5 dB, etc.). Additionally, Claim 3 introduces the rib waveguide cross-section limitation, which Takahashi also fails to disclose.
Conclusion: Takahashi does not anticipate Claim 3 of the '847 Patent.
III.A.3. Claim 5 of the '847 Patent
Full Claim Text:
5. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a plurality of thermal tuning elements, each thermal tuning element disposed in thermal contact with a respective one of the at least eight optical input waveguides, each thermal tuning element configured to adjust the effective refractive index of its respective optical input waveguide to tune the wavelength of the optical signal received by that waveguide.
Claim 5 depends from Claim 1 and adds the requirement of thermal tuning elements disposed in thermal contact with each input waveguide. These thermal tuning elements enable active wavelength tuning by adjusting the effective refractive index of the waveguide through localized heating.
Analysis: Takahashi does not disclose any thermal tuning mechanism. Takahashi's AWG device is entirely passive — it relies on fixed path-length differences to achieve wavelength separation and does not incorporate any active tuning capability. There is no mention of heaters, thermo-optic tuning, or any mechanism for adjusting the refractive index of the waveguides. Takahashi explicitly states that the device is designed to operate at fixed channel wavelengths determined by the AWG geometry (Takahashi at § II, p. 474), and notes that wavelength drift due to fabrication variability "remains a challenge" (Takahashi at § IV, p. 476) without proposing any solution.
Because Claim 5 depends from Claim 1, it incorporates all of the limitations of Claim 1 that Takahashi fails to disclose. Additionally, the thermal tuning element limitation of Claim 5 is entirely absent from Takahashi.
Conclusion: Takahashi does not anticipate Claim 5 of the '847 Patent.
III.A.4. Claim 9 of the '847 Patent
Full Claim Text:
9. A multi-channel silicon photonic waveguide multiplexer, comprising:
(a) means for receiving at least eight optical signals at distinct wavelengths within the C-band;
(b) means for combining the at least eight optical signals onto a single output waveguide on a silicon-on-insulator substrate with an insertion loss of less than 1.5 dB per channel; and
(c) means for mode-matching at each waveguide interface within the multiplexer to minimize optical loss at each interface.
Note Regarding Means-Plus-Function Claim: Claim 9 contains terms that invoke 35 U.S.C. § 112(f) — specifically, the phrases "means for receiving," "means for combining," and "means for mode-matching." Pursuant to the Means-Plus-Function Analysis Memorandum prepared by counsel and reviewed by me, these terms are construed to cover the corresponding structures disclosed in the specification and equivalents thereof:
• "Means for receiving": The corresponding structure is the plurality of at least eight optical input waveguides with rib or strip cross-sections as disclosed in the specification at col. 4, ll. 18-35, and Fig. 2A.
• "Means for combining": The corresponding structure is the waveguide combining region with cascaded multimode interference (MMI) couplers as disclosed in the specification at col. 5, ll. 1-28, and Fig. 3.
• "Means for mode-matching": The corresponding structure is the plurality of adiabatic waveguide tapers with the specific taper ratios and lengths disclosed in the specification at col. 6, ll. 5-30, and Fig. 4A-4C.
Analysis: Takahashi does not disclose the corresponding structures for any of the three means-plus-function limitations in Claim 9.
For the "means for receiving" limitation, Takahashi discloses four (not at least eight) input waveguides. For the "means for combining" limitation, Takahashi uses a star coupler (slab waveguide) architecture, not the cascaded MMI coupler structure identified as the corresponding structure in the '847 Patent specification. These are fundamentally different optical combining architectures — star couplers rely on spatial dispersion in a slab region, while MMI couplers exploit self-imaging in multimode waveguide sections. For the "means for mode-matching" limitation, Takahashi does not disclose any adiabatic waveguide taper or mode-matching structure, let alone the specific taper geometry identified as the corresponding structure.
Conclusion: Takahashi does not disclose the corresponding structures for the means-plus-function limitations of Claim 9. Takahashi does not anticipate Claim 9 of the '847 Patent.
III.A.5. Claim 14 of the '847 Patent
Full Claim Text:
14. A method of manufacturing a multi-channel silicon photonic waveguide multiplexer, comprising:
(a) providing a silicon-on-insulator wafer having a silicon device layer with a thickness between 200 nm and 280 nm on a buried oxide layer with a thickness between 1 μm and 3 μm;
(b) patterning, by electron-beam lithography or deep-ultraviolet photolithography, the silicon device layer to define at least eight optical input waveguides, a waveguide combining region, and a single output waveguide;
(c) forming a plurality of adiabatic waveguide tapers at each interface between each optical input waveguide and the waveguide combining region, each adiabatic waveguide taper having a taper ratio of at least 5:1 and a taper length of at least 50 μm;
(d) etching the patterned silicon device layer using a reactive-ion etching process to form the waveguides, the waveguide combining region, and the adiabatic waveguide tapers; and
(e) depositing a silicon dioxide cladding layer over the etched structures, the silicon dioxide cladding layer having a thickness between 1 μm and 2 μm.
Claim 14 is an independent method claim directed to the process of manufacturing the multi-channel waveguide multiplexer. It incorporates many of the same structural requirements as Claim 1 (at least eight channels, SOI substrate with specified layer thicknesses, adiabatic tapers with specified geometry) and adds specific fabrication process steps (electron-beam lithography or DUV photolithography, reactive-ion etching, and cladding deposition).
Analysis: Takahashi fails to disclose the method of Claim 14 for multiple reasons. First, Takahashi does not teach the fabrication of a device with at least eight input waveguides. Second, Takahashi does not describe the formation of adiabatic waveguide tapers at any stage of the fabrication process. Third, while Takahashi generally describes fabrication on an SOI platform, it does not specify the buried oxide layer thickness within the claimed range. Fourth, Takahashi does not disclose the specific patterning techniques (electron-beam lithography or DUV photolithography) required by step (b), as Takahashi used conventional i-line photolithography (Takahashi at § II, p. 474). Fifth, Takahashi does not disclose the silicon dioxide cladding layer thickness range specified in step (e).
Conclusion: Takahashi does not anticipate Claim 14 of the '847 Patent.
III.A.6. Summary — Takahashi Does Not Anticipate Any Asserted Claim of the '847 Patent
The following table summarizes the missing limitations for each asserted claim of the '847 Patent with respect to Takahashi (R-1):
At a minimum, the low insertion loss requirement, the channel count and spacing requirement, and the adiabatic waveguide taper/mode-matching structure are missing across every asserted claim. Takahashi describes a fundamentally different device — a 4-channel, passive AWG multiplexer with no taper structures and more than twice the insertion loss claimed in the '847 Patent. Takahashi does not anticipate any asserted claim of the '847 Patent.
III.B. Reference R-3: PCT/EP2015/071234 (Simonsen) (September 17, 2015)
Full Citation: International Patent Application PCT/EP2015/071234 (Simonsen et al.), "Wavelength Division Multiplexing Device for Optical Communication Systems," published March 23, 2016 (WO 2016/044238 A1). Filed September 17, 2015.
Theory Asserted by Lumicore: Obviousness under 35 U.S.C. § 103, both alone and in combination with Takahashi (R-1).
Date of Reference: September 17, 2015 (filing date). The reference pre-dates the '847 Patent's filing date of September 14, 2016, and qualifies as prior art under 35 U.S.C. § 102(a)(2).
Summary of Simonsen: Simonsen describes a wavelength division multiplexing device fabricated on an indium phosphide (InP) substrate, not a silicon-on-insulator (SOI) platform. The device uses an Echelle diffraction grating architecture to combine up to 16 wavelength channels in the C-band. Simonsen reports insertion loss of approximately 2.0–2.5 dB per channel. The device includes tapered waveguide transitions at the input/output interfaces, but these tapers are designed for the InP material system and have different geometric parameters than those claimed in the '847 Patent. Simonsen does not address silicon photonic integration, and the design principles and dimensional parameters specific to InP-based devices are not directly transferable to SOI platforms due to fundamental differences in refractive index contrast, waveguide dimensions, and mode profiles.
III.B.1. Claim 1 of the '847 Patent
Obviousness Analysis — Simonsen Alone: Simonsen alone does not render Claim 1 obvious because Simonsen fails to disclose the SOI substrate, the specific taper geometry, and the insertion loss performance. The mere existence of a WDM device on a different material platform does not render obvious a specifically designed SOI-based device with the claimed structural and performance parameters. A POSITA would not have looked to Simonsen's InP-based design as a blueprint for creating the claimed SOI device because the fundamental design parameters differ between the two material systems. The refractive index contrast in SOI (~2.0) is approximately six to seven times greater than in InP/InGaAsP (~0.3), which means that waveguide dimensions, taper geometries, mode profiles, and coupling architectures must be completely redesigned when transitioning between platforms. Simonsen's specific taper design is tailored to InP and would not function as intended on an SOI platform without substantial redesign — redesign that Simonsen does not teach or suggest.
Obviousness Analysis — Takahashi + Simonsen Combination: Lumicore asserts that the combination of Takahashi (R-1) and Simonsen (R-3) renders Claim 1 obvious, arguing that a POSITA would have taken Takahashi's silicon photonic AWG multiplexer and added Simonsen's tapered waveguide transitions to achieve lower insertion loss.
I disagree with this combination for multiple reasons:
(1) No motivation to combine: A POSITA would not have been motivated to combine a silicon photonic AWG reference (Takahashi) with an InP-based Echelle grating reference (Simonsen). These references disclose different material systems, different multiplexer architectures (AWG vs. Echelle grating), and different design approaches. A POSITA seeking to improve the insertion loss of Takahashi's silicon AWG would have looked to silicon-photonic-specific solutions, not to an InP-based design with an incompatible material system.
(2) Teaching away: Simonsen's disclosure is specific to the InP material system and cannot be straightforwardly applied to silicon photonic devices. The references effectively teach away from each other because they represent different design paradigms optimized for different material platforms. Simonsen's taper design (3:1 ratio, 30 μm length) would not achieve adiabatic mode-matching in a high-index-contrast SOI waveguide, where much larger taper ratios and longer taper lengths are needed to avoid scattering losses at mode transitions.
(3) No reasonable expectation of success: Even if a POSITA were to attempt to combine elements of both references, there would be no reasonable expectation of success in achieving the claimed insertion loss of less than 1.5 dB per channel. Takahashi's AWG architecture inherently suffers from phase errors and diffraction losses that are not addressed by simply adding tapered transitions. Simonsen's tapers, even if scaled for SOI, do not meet the claimed geometric parameters and would not overcome the fundamental loss mechanisms in Takahashi's AWG design.
(4) Missing limitations remain: Even if the combination were permissible, it would still not disclose all claim limitations. The resulting hypothetical device would combine Takahashi's 4-channel AWG with modified tapers — but the claim requires at least eight channels with ≤200 GHz spacing, a requirement that neither reference teaches in the context of the combined device.
Conclusion for Claim 1: Simonsen, alone or in combination with Takahashi, does not render Claim 1 of the '847 Patent obvious under 35 U.S.C. § 103.
III.B.2–III.B.5. Claims 3, 5, 9, 14
The analysis of Simonsen against Claims 3, 5, 9, and 14 of the '847 Patent follows the same framework as Claim 1, with additional deficiencies identified for each claim's specific limitations.
Claim 3: Simonsen does not disclose the rib waveguide cross-section geometry required by Claim 3 (rib height 150–220 nm, slab height 50–90 nm, rib width 400–600 nm). Simonsen's InP waveguides have ridge (not rib) cross-sections with dimensions scaled for the InP material system, including a ridge height of approximately 1.5 μm and a ridge width of approximately 2.5 μm — well outside the claimed ranges that are specific to SOI waveguides. In addition to all missing limitations from Claim 1, the rib waveguide geometry of Claim 3 is not taught by Simonsen. Conclusion: Simonsen does not render Claim 3 obvious, alone or in combination with Takahashi.
Claim 5: Simonsen does not disclose thermal tuning elements. While Simonsen briefly mentions the potential for thermoelectric coolers to stabilize the InP Echelle grating (Simonsen at [0045]), this is a bulk chip-level temperature stabilization approach, not the individual per-waveguide thermal tuning elements required by Claim 5. Simonsen does not teach tuning elements "disposed in thermal contact with a respective one of the at least eight optical input waveguides" or elements "configured to adjust the effective refractive index of its respective optical input waveguide." Conclusion: Simonsen does not render Claim 5 obvious, alone or in combination with Takahashi.
Claim 9: Simonsen does not disclose the corresponding structures for the means-plus-function limitations of Claim 9. Simonsen's Echelle grating is structurally and functionally distinct from the cascaded MMI coupler structure identified as the corresponding structure for the "means for combining" limitation. Simonsen's tapers, as discussed above, do not match the corresponding structure for the "means for mode-matching" limitation. Conclusion: Simonsen does not render Claim 9 obvious, alone or in combination with Takahashi.
Claim 14: Simonsen does not disclose a method of manufacturing an SOI-based device. Simonsen's fabrication methods are specific to InP epitaxial growth and processing (MOVPE, wet-chemical etching) and bear no resemblance to the SOI fabrication process of Claim 14 (electron-beam or DUV lithography on an SOI wafer, reactive-ion etching, SiO₂ cladding deposition). Conclusion: Simonsen does not render Claim 14 obvious, alone or in combination with Takahashi.
III.B.6. Summary — Simonsen (Alone or in Combination) Does Not Render Any Asserted Claim Obvious
Simonsen is an InP-based reference that operates in a fundamentally different material system from the silicon-on-insulator platform of the '847 Patent. The reference fails to disclose the SOI substrate, the claimed taper geometry, the claimed insertion loss, and numerous other limitations. The proposed combination of Takahashi + Simonsen lacks motivation to combine, teaches away from the claimed invention, and offers no reasonable expectation of success. Neither Simonsen alone nor the Takahashi + Simonsen combination renders any asserted claim of the '847 Patent obvious.
III.C. Reference R-6: Ohtani et al., "Low-Loss Silicon Photonic Wavelength Multiplexer for Datacenter Interconnects," Japanese Journal of Applied Physics (January 2015)
Theory Asserted by Lumicore: Anticipation under 35 U.S.C. § 102.
Date of Reference: January 2015. Pre-dates the '847 Patent's filing date of September 14, 2016.
Summary of Ohtani: Ohtani et al. describe a silicon photonic cascaded Mach-Zehnder interferometer (MZI) wavelength multiplexer fabricated on an SOI platform with a 220 nm silicon device layer on a 2 μm buried oxide layer. The device supports four (4) WDM channels with 800 GHz channel spacing. Ohtani reports insertion loss of approximately 1.8 dB per channel. The device does not include adiabatic waveguide tapers; instead, it uses directional coupler-based combiner stages. Ohtani does not address scaling to eight or more channels and does not discuss thermal tuning elements.
Claim-by-Claim Analysis: Ohtani fails to disclose several critical limitations of Claims 1, 3, 5, 9, and 14. Specifically:
• Claim 1: Ohtani discloses only four channels (not at least eight), with 800 GHz spacing (not ≤200 GHz). Ohtani does not disclose adiabatic waveguide tapers or mode-matching structures. Ohtani's insertion loss of 1.8 dB exceeds the claimed 1.5 dB maximum. While Ohtani does disclose an SOI substrate with layer thicknesses within the claimed ranges (220 nm silicon, 2 μm box), at least three other limitations are missing.
• Claim 3: Ohtani uses strip (not rib) waveguides. The rib waveguide cross-section geometry is missing.
• Claim 5: Ohtani does not disclose thermal tuning elements.
• Claim 9: Ohtani does not disclose the corresponding structures for the means-plus-function limitations (cascaded MMI couplers, adiabatic tapers).
• Claim 14: Ohtani does not describe the claimed fabrication method steps, including the formation of adiabatic tapers and the specific cladding thickness.
Conclusion: Ohtani does not anticipate any asserted claim of the '847 Patent.
III.D. Reference R-7: U.S. Patent No. 8,947,013 (Ranganath) (February 2015)
Theory Asserted by Lumicore: Obviousness under 35 U.S.C. § 103 (asserted in combination with R-1 and R-6).
Date of Reference: February 3, 2015.
Summary of Ranganath: Ranganath discloses a silicon photonic multiplexer with integrated thin-film heaters for thermal tuning. The device has four channels with 200 GHz spacing on an SOI platform. Ranganath's heaters are resistive thin-film elements patterned on the waveguide cladding. However, Ranganath's device uses a micro-ring resonator-based multiplexer architecture, not the waveguide combining region with adiabatic tapers claimed in the '847 Patent. Ranganath reports insertion loss of approximately 2.8 dB per channel.
Claim-by-Claim Analysis:
• Claim 1: Ranganath discloses only four channels (missing ≥8). Channel spacing of 200 GHz meets the ≤200 GHz requirement. However, Ranganath does not disclose the waveguide combining region, adiabatic tapers, or insertion loss below 1.5 dB. The micro-ring resonator architecture is fundamentally different from the claimed waveguide combining structure.
• Claim 5: Ranganath discloses thermal tuning elements (heaters on waveguides), which is relevant to the Claim 5 limitation. However, Ranganath's heaters are disposed on micro-ring resonators, not on "optical input waveguides" as required by Claim 5. Moreover, because Claim 5 depends from Claim 1, all of Claim 1's missing limitations remain.
• Claims 3, 9, 14: Additional missing limitations as noted above.
Obviousness Combinations:
• Ranganath + Takahashi: A POSITA would not have combined a micro-ring resonator multiplexer (Ranganath) with an AWG multiplexer (Takahashi) because these are competing architectures with incompatible design principles. There is no motivation to combine, and no reasonable expectation of success in achieving the claimed waveguide combining region with adiabatic tapers from either reference.
• Ranganath + Ohtani: Similarly, combining Ranganath's micro-ring design with Ohtani's cascaded MZI design would not yield the claimed invention. The resulting combination would still lack the adiabatic taper structure, the ≥8 channel count, and the sub-1.5 dB insertion loss.
Conclusion: Ranganath, alone or in combination with Takahashi or Ohtani, does not render any asserted claim of the '847 Patent obvious.
III.E. Reference R-8: Chang & Patel, ECOC 2014 Conference Paper (September 2014)
Theory Asserted by Lumicore: Obviousness under 35 U.S.C. § 103 (in combination with R-1).
Date of Reference: September 2014.
Summary of Chang & Patel: This conference paper discusses broadband waveguide coupler designs for photonic integration, including tapered mode-size converters for coupling between dissimilar waveguide sections. The paper presents simulation results for several taper designs, including adiabatic tapers with various taper ratios and lengths. However, the tapers discussed are for fiber-to-chip coupling applications, not for intra-chip waveguide-to-combiner interfaces. The paper does not describe a multiplexer device, does not address channel count or wavelength spacing, and does not report insertion loss for any multiplexer configuration.
Claim-by-Claim Analysis:
• Claim 1: Chang & Patel do not disclose a multi-channel waveguide multiplexer. The reference addresses fiber-to-chip coupling, not wavelength multiplexing. Missing limitations include the multiplexer structure, channel count, channel spacing, SOI substrate specifications, and insertion loss performance. While Chang & Patel discuss adiabatic tapers with ratios up to 8:1 and lengths up to 200 μm, these tapers serve a different function (fiber-chip coupling) and are not disposed "at each interface between each of the at least eight optical input waveguides and the waveguide combining region" as required by the claim.
• Combination R-8 + R-1 (Chang & Patel + Takahashi): Lumicore argues that a POSITA would have added Chang & Patel's adiabatic tapers to Takahashi's AWG multiplexer. However, Chang & Patel's tapers are designed for fiber-to-chip interfaces, not for waveguide-to-star-coupler interfaces within an AWG. A POSITA would recognize that the mode-matching requirements at these two types of interfaces are fundamentally different — fiber-to-chip coupling involves a mode-field diameter mismatch of approximately 10 μm to 0.5 μm, while intra-chip waveguide interfaces involve much smaller mismatches. Applying Chang & Patel's fiber-coupling tapers at AWG internal interfaces would be physically inappropriate. Moreover, even if such tapers were applied, the combination would still fail to address Takahashi's 4-channel limitation and would not achieve the sub-1.5 dB insertion loss, because the dominant loss mechanism in AWGs is phase error and diffraction, not mode mismatch.
Conclusion: Chang & Patel, alone or in combination with Takahashi, does not render any asserted claim of the '847 Patent obvious. The reference is asserted only against Claims 1, 9, and 14 and fails as to all three.
III.F. Reference R-9: JP 2015-048221 (Yamamoto) (March 2015)
Theory Asserted by Lumicore: Anticipation under 35 U.S.C. § 102.
Date of Reference: March 16, 2015.
Summary of Yamamoto: This Japanese patent application describes a silicon photonic device with a "wavelength combining function" using a planar concave grating (PCG) architecture on an SOI platform. The device combines four wavelength channels onto a single output waveguide. Yamamoto discloses waveguide tapers at the grating input interface, but these are linear (non-adiabatic) tapers with a taper ratio of approximately 2:1 and a length of 20 μm. The reported insertion loss is approximately 2.5 dB per channel. Yamamoto does not discuss scaling beyond four channels or reducing channel spacing below 400 GHz.
Claim-by-Claim Analysis:
• Claim 1: Yamamoto discloses only four channels (not ≥8), with 400 GHz spacing (not ≤200 GHz). Yamamoto's tapers are non-adiabatic (linear) with a 2:1 ratio and 20 μm length — far below the required 5:1 ratio and 50 μm minimum. Insertion loss of 2.5 dB exceeds the 1.5 dB maximum. SOI layer thicknesses are not fully specified.
• Claims 3, 5, 14: Additional missing limitations consistent with the analysis of other references.
Conclusion: Yamamoto does not anticipate any asserted claim of the '847 Patent.
III.G. Claim Differentiation Considerations for '847 Patent
Lumicore has argued in its invalidity contentions that independent Claim 1 of the '847 Patent should be construed more narrowly in light of dependent Claims 3 and 5. Specifically, Lumicore contends that because Claim 3 adds a rib waveguide cross-section and Claim 5 adds thermal tuning elements, Claim 1 should be read as broadly as possible to exclude these features — and that, under such a broad reading, certain prior-art references might disclose the limitations of Claim 1.
I have considered this argument and conclude that it does not affect my analysis. The doctrine of claim differentiation creates a rebuttable presumption that dependent claims are narrower than independent claims, but it does not require that independent claims be read to encompass all prior art. Even applying Lumicore's argument — and reading Claim 1 as broadly as possible while still consistent with the specification — the prior-art references cited against the '847 Patent still fail to disclose the adiabatic waveguide taper structure with the specific geometric parameters (5:1 taper ratio, 50 μm minimum length), the channel count (≥8), the channel spacing (≤200 GHz), and the insertion loss performance (<1.5 dB per channel). These limitations are present in Claim 1 itself, not added by dependent claims, and none of the prior-art references discloses all of them.
This analysis is consistent with the claim differentiation discussion in the internal Calderwood & Harkness memorandum on claim differentiation, which I have reviewed and concur with to the extent it addresses the technical merits.
IV. PRIOR ART CLAIM CHARTS — '193 PATENT (U.S. Patent No. 10,891,193)
"High-Bandwidth Coherent Optical Transceiver Integrated on Silicon Substrate"
Patent Information:
• Filing Date: April 7, 2017
• Priority: Provisional Application No. 62/499,117, filed April 7, 2017
• Issue Date: January 12, 2021
• Inventors: Dr. James M. Harrington, Dr. Priya S. Venkataraman, Dr. Michael T. Reeves
• Original and Current Assignee: Optiwave Semiconductor Corp.
• Family Relationship: Shares Provisional Application No. 62/499,117 with the '015 Patent
• Asserted Claims: 1, 3, 7, 10, 15, 18
• Total Prior-Art References Asserted Against '193 Patent: 8 (References R-1, R-10, R-11, R-12, R-13, R-14, R-15, R-16)
The '193 Patent is directed to a high-bandwidth coherent optical transceiver monolithically integrated on a silicon substrate. The patent addresses the industry challenge of integrating all functional components of a coherent transceiver — including coherent modulator, coherent receiver with 90-degree optical hybrids, local oscillator interface, polarization management, and digital signal processing interface — onto a single silicon photonic chip. Prior to the '193 Patent, coherent transceivers were typically assembled from discrete InP-based photonic components and silicon electronic components, resulting in larger footprints, higher power consumption, and reduced reliability. The '193 Patent achieves monolithic integration of these functions on a silicon substrate through innovative design architectures for the coherent detection module and modulator sections.