PRIVILEGED AND CONFIDENTIAL ATTORNEY-CLIENT PRIVILEGED ATTORNEY WORK PRODUCT
MEMORANDUM
TO: Nathaniel Bower, Responsible Partner, Calderwood & Harkness LLP Patricia Langford, General Counsel, Optiwave Semiconductor Corp.
FROM: Megan Chu, Lead Associate, Calderwood & Harkness LLP Derek Okonkwo, Working Associate, Calderwood & Harkness LLP
DATE: May 28, 2025
RE: H-1B Cap Petition Strategy — FY2026 Selected Candidates (Optiwave Semiconductor Corp.)
MATTER REFERENCE: SC-OWS-2025-0520-IMM
CC: Dr. Lena Marchetti, Of Counsel, Calderwood & Harkness LLP Rajesh Anand, Immigration Program Manager, Optiwave Semiconductor Corp. Tanya Benavides, Paralegal, Calderwood & Harkness LLP
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I. Executive Summary
This memorandum sets forth the filing strategy for the five FY2026 H-1B cap-subject candidates selected in the April 1, 2025 lottery, and addresses alternative pathways for the four candidates who were not selected. The memorandum is intended to provide Optiwave Semiconductor Corp. ("OWS" or the "Company") and the Calderwood & Harkness engagement team with a comprehensive roadmap encompassing case strategy, prevailing wage compliance, filing logistics, budgeting, and coordination with related pending immigration matters.
On March 7, 2025, OWS submitted H-1B registrations for nine cap-subject candidates through the USCIS online registration system. USCIS lottery results announced on April 1, 2025 confirmed that five of the nine candidates were selected for FY2026 cap-subject H-1B petitions. The remaining four candidates were not selected and require alternative strategy development, as discussed in Section XIII below.
The filing window for selected registrants runs sixty days from the April 1, 2025 selection date, yielding an absolute filing deadline of June 30, 2025. Our target is to begin filing petitions with the USCIS California Service Center no later than June 25, 2025, providing a five-day buffer to account for any unforeseen delays in documentation gathering or delivery logistics.
All five petitions will be filed with Premium Processing (Form I-907), at a cost of $2,805 per petition, to ensure adjudication within the fifteen-calendar-day window mandated by the Premium Processing Service. Total government fees per cap petition amount to $5,650, calculated as follows: $780 (I-129 base filing fee) + $215 (H-1B registration fee, already paid at registration) + $500 (Fraud Prevention and Detection Fee) + $750 (ACWIA Fee) + $600 (Asylum Program Fee) + $2,805 (Premium Processing Fee). Calderwood & Harkness legal fees are capped at $6,500 per H-1B cap petition pursuant to the engagement letter executed under Matter Reference SC-OWS-2025-0520-IMM.
All five candidates are currently maintaining F-1 nonimmigrant status with employment authorization under either Optional Practical Training ("OPT") or OPT STEM Extension. Each petition will request a change of status from F-1 to H-1B effective October 1, 2025, the first day of FY2026 and the earliest permissible start date for cap-subject H-1B petitions. The cap-gap provisions under 8 CFR § 214.2(f)(5)(vi) will automatically extend each candidate's F-1 OPT or STEM OPT status and employment authorization through September 30, 2025 (or the date of adjudication, if earlier), provided the H-1B petition is timely filed.
OWS is a non-H-1B-dependent employer within the meaning of INA § 212(n)(1)(E)–(G). Currently, OWS employs fourteen H-1B workers out of a total workforce of approximately 340 employees, representing an H-1B dependency ratio of 4.12% — well below the 15% threshold that triggers additional attestation obligations. Even after the addition of five new H-1B workers, OWS's H-1B dependency ratio will be approximately 5.59% (19 out of 340), remaining comfortably below the statutory threshold. Accordingly, OWS is not subject to the enhanced attestation requirements regarding non-displacement and secondary displacement of U.S. workers, nor the recruitment attestation obligations imposed on H-1B-dependent employers.
We note the transition context in which these filings are taking place. OWS's immigration counsel transitioned from Whitfield & Parekh LLP (engagement concluded April 30, 2025) to Calderwood & Harkness LLP (engagement opened May 20, 2025). A formal file transfer request was transmitted to Kavita Parekh at Whitfield & Parekh LLP on May 22, 2025, and we have targeted completion of the file transfer by June 15, 2025. LCA and petition preparation are proceeding in parallel with the file transfer to ensure that the June 30 deadline is met regardless of the file transfer timeline.
II. Client Overview
Petitioner: Optiwave Semiconductor Corp. ("OWS"), a Delaware corporation qualified to do business in California, Texas, and Oregon.
Headquarters: 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
Employer Identification Number (FEIN): 82-4931076.
NAICS Code: 334413 (Semiconductor and Related Device Manufacturing).
Industry Focus: OWS is engaged in the design and fabrication of photonic integrated circuits ("PICs") for data center interconnects. The Company occupies a specialized niche within the semiconductor industry, leveraging silicon photonics and indium phosphide technologies to produce high-speed optical transceivers, modulators, and photodetectors that serve hyperscale data center operators and telecommunications infrastructure providers.
Date of Incorporation: March 14, 2017.
Employees: OWS employs approximately 340 individuals across its operations, distributed as follows:
• San Jose, CA (Site A — Headquarters): Approximately 210 employees, encompassing engineering, R&D, executive leadership, and administrative functions.
• Austin, TX (Site B): Approximately 65 employees, primarily design engineering and verification.
• Portland, OR (Site C): Approximately 40 employees, focused on packaging R&D and advanced manufacturing process development.
• Remote: Approximately 25 employees in various support functions.
Annual Revenue (FY2024): $187.4 million, as reported in the audited financial statements prepared by Pendleton Accounting Group LLP (audit partner: Marcus Hensley, CPA). This revenue figure reflects continued growth in the photonic interconnect market and demonstrates OWS's robust financial capacity to support the proffered wages for all H-1B beneficiaries.
Majority Shareholder: Crestline Ventures Fund IV, LP, which holds a 62.4% equity interest in OWS, acquired on September 15, 2022. The Managing Partner of Crestline Ventures is Howard Driscoll. The remaining equity is held by a combination of founding shareholders, management, and other institutional investors.
Key Client Contacts for this matter:
• Patricia Langford — General Counsel, OWS. Primary legal decision-maker for immigration matters. Authorized to provide filing approvals and execute engagement documents.
• Dr. Yun-Sheng Chen — Vice President of Engineering, OWS. Serves as the hiring manager for all five positions and will provide technical attestations and sign employer support letters for each petition.
• Samantha Kowalski — Director of Human Resources, OWS. Responsible for I-9 compliance, onboarding procedures, and coordination with payroll for H-1B wage compliance.
• Rajesh Anand — Immigration Program Manager, OWS. Day-to-day coordinator for all immigration matters, responsible for document collection from beneficiaries, intranet LCA posting, E-Verify compliance, and liaison between OWS and Calderwood & Harkness.
E-Verify Company ID: 1487623. OWS is enrolled in the E-Verify program and maintains active participation, as required for employers of STEM OPT workers under 8 CFR § 274a.12(c)(3)(i)(C). E-Verify case management is supported by Sentinel Background Verification Corp. (contact: Tyler Ng).
H-1B Dependency Status: OWS is classified as a non-H-1B-dependent employer. With 14 current H-1B workers out of a total workforce of 340 employees, the dependency ratio is 4.12%. The statutory threshold for H-1B dependency under INA § 212(n)(1)(E)(ii) is 15% for employers with 51 or more full-time equivalent employees. OWS is far below this threshold.
Current visa Portfolio: OWS currently sponsors 18 active nonimmigrant visa holders:
• 14 H-1B workers
• 3 O-1A (Extraordinary Ability in Sciences) visa holders
• 1 O-1B (Extraordinary Ability in Arts) visa holder
Following approval of the five pending cap petitions, OWS's H-1B headcount will increase to 19, and its total visa-sponsored workforce will number 23.
III. FY2026 H-1B Registration and Lottery Results
A. Registration Filing
OWS submitted H-1B registrations for nine cap-subject candidates via the USCIS online registration system on March 7, 2025, during the FY2026 initial registration period. The H-1B registration fee of $215 per beneficiary was paid by OWS for all nine candidates, totaling $1,935 in registration fees. Registrations were submitted by Whitfield & Parekh LLP, which was OWS's immigration counsel at the time.
All nine candidates were classified as cap-subject. None of the candidates qualified for cap-exempt status under INA § 214(c)(1) (i.e., none were to be employed at a qualifying institution of higher education, affiliated nonprofit research organization, or governmental research organization). All nine candidates hold F-1 nonimmigrant status with OPT or STEM OPT employment authorization issued based on degrees from U.S. institutions of higher education.
B. Lottery Results (April 1, 2025)
USCIS announced the results of the FY2026 H-1B lottery on April 1, 2025. Of OWS's nine registered candidates, five were selected and four were not selected:
Selected (5):
1. Naveen Sharma — Photonics Process Engineer
2. Yuki Tanaka — Analog Design Engineer
3. Ekaterina Solovyova — Verification Engineer
4. Ahmed Hassan — Thermal Engineer
5. Min-Jun Lee — EDA Tools Developer
Not Selected (4):
1. Carlos Delgado Rivera — MEMS Process Engineer
2. Anh Nguyen — Packaging R&D Engineer
3. Blessing Adeyemi — Test Engineer
4. Sofia Petrova — Fiber Coupling Engineer
The selection rate of 55.6% (5 of 9) is broadly consistent with historical lottery selection rates in recent fiscal years, though individual outcomes are inherently stochastic. The non-selected candidates are discussed in Section XIII below.
C. Filing Window
The selection date for all five candidates is April 1, 2025. Under current USCIS policy, selected registrants have a sixty-day filing window from the date of selection notification to submit H-1B cap petitions. This window runs through June 30, 2025, which constitutes the absolute filing deadline.
Our target is to commence filing petitions on June 25, 2025, providing a five-day cushion before the deadline. This target accounts for the time required to complete LCA certification, document assembly, quality control review, and overnight delivery logistics.
All five petitions will be filed with the USCIS California Service Center, located at 24000 Avila Road, Laguna Niguel, CA 92677, which is the designated filing location for H-1B cap petitions when the petitioner's principal place of business is in California.
Premium Processing has been elected for all five petitions. Pursuant to the Premium Processing Service, USCIS is required to adjudicate each petition within fifteen calendar days of receipt, or issue a Request for Evidence ("RFE"), Notice of Intent to Deny ("NOID"), or approval/denial notice within that period.
The requested H-1B start date for all five petitions is October 1, 2025, the first day of FY2026 and the earliest permissible start date for cap-subject H-1B employment.
IV. Individual Candidate Analysis — Selected Candidates
This section provides a detailed analysis of each of the five selected candidates, covering biographical and immigration status information, the proposed position and SOC code assignment, prevailing wage and offered compensation, specialty occupation analysis, and filing considerations specific to each candidate.
A. Naveen Sharma — Photonics Process Engineer
1. Biographical and Immigration Status
Current Immigration Status: F-1 Optional Practical Training (OPT).
Institutional Affiliation: Naveen Sharma holds a Bachelor of Technology (B.Tech.) degree from the Indian Institute of Technology Madras (IIT Madras). We note that OPT employment authorization is issued by USCIS based on the recommendation of a Designated School Official ("DSO") at a SEVP-certified U.S. institution. Accordingly, it is critical to confirm whether Mr. Sharma completed an additional degree program at a U.S. institution that forms the basis of his OPT authorization, or whether his OPT was authorized through a U.S. institution at which he was enrolled in a different capacity (e.g., a graduate program). We must verify the underlying I-20 and EAD validity to ensure that Mr. Sharma's OPT is properly predicated on a qualifying U.S. degree program. Derek Okonkwo will coordinate with Rajesh Anand to obtain copies of Mr. Sharma's I-20, EAD card, and SEVIS record to confirm these details.
Proposed Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
2. Position and SOC Code
Position Title: Photonics Process Engineer
SOC Code: 17-2199.08 (Photonics Engineers), which maps to the broader occupational classification 17-2199, Engineers, All Other, for prevailing wage determination purposes. This SOC code is appropriate because the role involves the engineering of photonic devices and systems, which does not fall neatly within a more specific engineering SOC code such as Electrical Engineers (17-2071) or Electronics Engineers (17-2072). The "All Other" category captures the interdisciplinary nature of photonics engineering, which draws on optics, semiconductor physics, materials science, and electrical engineering.
Minimum Education Requirement: Bachelor's degree in Photonics Engineering, Electrical Engineering, Physics, or a closely related field.
Position Duties: The Photonics Process Engineer will be responsible for the following duties:
• Development and optimization of fabrication processes for photonic integrated circuits ("PICs"), including lithography, etching, thin-film deposition, and chemical-mechanical planarization;
• Yield optimization through statistical process control, defect analysis, and root cause investigation;
• Cleanroom process qualification and equipment characterization for new and existing process modules;
• Wafer-level testing and optical characterization of PIC devices, including insertion loss, extinction ratio, and bandwidth measurements;
• Collaboration with the design engineering team on design-for-manufacturability ("DFM") initiatives, providing process feedback to inform design rule development;
• Documentation of process specifications, equipment recipes, and standard operating procedures;
• Participation in failure analysis and corrective action processes.
3. Prevailing Wage and Offered Compensation
Prevailing Wage: SOC 17-2199, Level III (Experienced), San Jose-Sunnyvale-Santa Clara Metropolitan Statistical Area ("MSA"): $152,506 per year.
Offered Compensation: IC3 level — $175,000 base salary plus $30,000 per year in Restricted Stock Units ("RSUs"), for a total annualized compensation of $205,000.
Wage Differential: The offered compensation exceeds the applicable prevailing wage by $52,494 (34.4% above the prevailing wage), demonstrating robust prevailing wage compliance.
4. Specialty Occupation Analysis
The Photonics Process Engineer position satisfies the definition of a "specialty occupation" under INA § 214(i)(1) and the regulatory criteria set forth at 8 CFR § 214.2(h)(4)(ii). Specifically:
(i) Bachelor's Degree Normally Required. A bachelor's degree in photonics engineering, electrical engineering, physics, or a closely related field is the normal minimum requirement for entry into the position. The role demands a deep understanding of semiconductor fabrication physics, optical waveguide theory, and cleanroom process methodologies that can only be acquired through a structured academic program culminating in at least a bachelor's degree.
(ii) Degree Requirement Common in Industry. The degree requirement is common in the semiconductor and photonics industry for process engineering roles. Industry job postings from comparable employers (e.g., Hollowell Group Photonics, Quillon Industries, Drayton Group, Dunmore Industries) uniformly require at minimum a bachelor's degree in a relevant engineering or physical science discipline for process engineering positions.
(iii) Employer Normally Requires Degree. OWS has consistently required a bachelor's degree in a relevant engineering discipline for its process engineering positions. Historical hiring records and existing position descriptions confirm this longstanding practice.
(iv) Nature of Duties Is Specialized. The duties of the Photonics Process Engineer — including PIC fabrication process development, yield optimization, cleanroom process qualification, and wafer-level optical testing — are so specialized and complex that the knowledge required to perform them is usually associated with the attainment of a bachelor's or higher degree in a specific specialty.
The Bureau of Labor Statistics Occupational Outlook Handbook ("OOH") entry for Engineers, All Other, confirms that a bachelor's degree in engineering is the typical entry-level education requirement for engineers in miscellaneous specialties, further supporting the specialty occupation classification.
5. Filing Considerations
LCA Filing: A Labor Condition Application will be filed via the DOL FLAG system for the San Jose-Sunnyvale-Santa Clara MSA, specifying the worksite at 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134. Electronic posting on the OWS intranet for ten consecutive business days is required under 20 CFR § 655.734.
Government Fees: $5,650 ($780 + $215 + $500 + $750 + $600 + $2,805).
OPT Bridge: We must confirm that Mr. Sharma's F-1 OPT EAD remains valid through at least September 30, 2025, to bridge employment authorization to the October 1, 2025 H-1B start date. If Mr. Sharma's OPT expires before October 1, the cap-gap automatic extension under 8 CFR § 214.2(f)(5)(vi) will extend his F-1 status and employment authorization through September 30, 2025, provided the H-1B petition is timely filed.
Credential Evaluation: Because Mr. Sharma's undergraduate degree is from IIT Madras (an Indian institution), a credential evaluation from a NACES-member evaluation service will be required to establish the U.S. equivalency of his degree. Derek Okonkwo will coordinate the evaluation order.
B. Yuki Tanaka — Analog Design Engineer
1. Biographical and Immigration Status
Current Immigration Status: F-1 OPT STEM Extension.
Institutional Affiliation: University of Michigan, Ann Arbor. Ms. Tanaka holds a Master of Science in Electrical Engineering from the University of Michigan. Her STEM OPT Extension provides an additional twenty-four months of employment authorization beyond the initial twelve-month OPT period, providing extended bridge coverage through the cap-gap period.
Proposed Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
2. Position and SOC Code
Position Title: Analog Design Engineer
SOC Code: 17-2072 (Electronics Engineers, Except Computer). This SOC code is appropriate because the Analog Design Engineer role involves the design and development of analog and mixed-signal integrated circuits, which falls squarely within the occupational definition for Electronics Engineers.
Minimum Education Requirement: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a closely related field.
Position Duties: The Analog Design Engineer will perform the following duties:
• Design of analog and mixed-signal integrated circuits for PIC driver circuits, transimpedance amplifiers ("TIAs"), and clock-data recovery ("CDR") circuits;
• SPICE simulation and modeling of analog circuit performance, including noise analysis, linearity characterization, and temperature sensitivity evaluation;
• Layout design of analog circuits in compliance with design rules and electromagnetic compatibility requirements;
• Coordination of tapeout schedules and liaison with foundry partners on fabrication specifications;
• Silicon validation and characterization of fabricated analog circuits, including bench testing, automated test equipment ("ATE") validation, and correlation analysis;
• Collaboration with photonics design engineers to ensure seamless electro-optical integration;
• Technical documentation and design review participation.
3. Prevailing Wage and Offered Compensation
Prevailing Wage: SOC 17-2072, Level III (Experienced), San Jose-Sunnyvale-Santa Clara MSA: $157,830 per year.
Offered Compensation: IC3 level — $175,000 base salary plus $30,000 per year in RSUs, for a total annualized compensation of $205,000.
Wage Differential: The offered compensation exceeds the applicable prevailing wage by $47,170 (29.9% above the prevailing wage).
4. Specialty Occupation Analysis
The Analog Design Engineer position presents a strong specialty occupation case. Electronics Engineers is a well-established specialty occupation under USCIS adjudicatory precedent, and the position readily satisfies all four regulatory criteria under 8 CFR § 214.2(h)(4)(ii):
A bachelor's degree in Electrical Engineering or Electronics Engineering is the industry-standard entry-level requirement for analog design engineer positions. This requirement is common across the semiconductor industry, is OWS's normal requirement for this role, and the duties are sufficiently specialized — involving advanced analog circuit design, SPICE simulation, and silicon validation — that the knowledge required is associated with attainment of a bachelor's or higher degree in the specific specialty.
The DOL OOH confirms that a bachelor's degree in electrical engineering, electronics engineering, or a related field is the typical entry-level education requirement for Electronics Engineers, further supporting the specialty occupation classification. Given the strength of this occupational classification, we assess the risk of a specialty occupation challenge as very low.
5. Filing Considerations
LCA Filing: LCA to be filed for the San Jose-Sunnyvale-Santa Clara MSA via the DOL FLAG system.
Government Fees: $5,650.
STEM OPT Bridge: Ms. Tanaka's STEM OPT Extension provides robust bridge coverage through the cap-gap period. The cap-gap automatic extension applies. OWS must ensure continued compliance with STEM OPT reporting obligations, including the annual validation report. E-Verify compliance for STEM OPT employment is maintained through OWS's E-Verify enrollment (Company ID 1487623), with case management support from Sentinel Background Verification Corp. (Tyler Ng).
Credential Evaluation: Not anticipated to be required, as Ms. Tanaka holds a U.S. master's degree from the University of Michigan.
C. Ekaterina Solovyova — Verification Engineer
1. Biographical and Immigration Status
Current Immigration Status: F-1 OPT STEM Extension.
Institutional Affiliation: University of California, Berkeley. Ms. Solovyova holds a Master of Science in Electrical Engineering and Computer Sciences from UC Berkeley. Her STEM OPT Extension provides extended coverage through the cap-gap period.
Proposed Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
2. Position and SOC Code
Position Title: Verification Engineer
SOC Code: 15-1252 (Software Developers). This SOC code is assigned because the Verification Engineer role involves significant software development activities, including testbench development in SystemVerilog and UVM. While the role is performed in a hardware engineering context (RTL verification for PIC-related ASICs), the SOC classification for Software Developers appropriately captures the primary occupational function. The alternative SOC code of 17-2072 (Electronics Engineers) was considered but rejected because the predominant duties involve software-centric verification methodologies rather than direct electronics hardware design.
Minimum Education Requirement: Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or a closely related field.
Position Duties: The Verification Engineer will perform the following duties:
• Register Transfer Level ("RTL") verification of digital control logic and signal processing blocks within PIC-related ASICs;
• Development and maintenance of SystemVerilog/Universal Verification Methodology ("UVM") testbenches for functional verification;
• Coverage analysis, including code coverage, functional coverage, and assertion-based verification metrics;
• Formal verification methodologies, including equivalence checking and model checking;
• Silicon bug triage and root cause analysis in collaboration with design engineers;
• Regression suite development and maintenance;
• Verification planning and documentation, including verification plan creation and closure reports.
3. Prevailing Wage and Offered Compensation
Prevailing Wage: SOC 15-1252, Level III (Experienced), San Jose-Sunnyvale-Santa Clara MSA: $168,272 per year.
Offered Compensation: IC3 level — $175,000 base salary plus $30,000 per year in RSUs, for a total annualized compensation of $205,000.
Wage Differential: The offered compensation exceeds the applicable prevailing wage by $36,728 (21.8% above the prevailing wage).
4. Specialty Occupation Analysis
The Verification Engineer position requires specialized knowledge in hardware verification methodologies, including SystemVerilog, UVM, and formal verification techniques, that can only be acquired through a structured academic program resulting in at least a bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science. The position satisfies the regulatory criteria under 8 CFR § 214.2(h)(4)(ii), and is consistent with the DOL OOH entry for Software Developers and Software Quality Assurance Analysts and Testers, which confirms a bachelor's degree as the typical entry-level requirement.
OWS's specific duty set — involving SystemVerilog/UVM testbench development, formal verification, and silicon bug triage for PIC-related ASICs — strongly supports the specialty occupation classification. The position requires not a generalized software development skill set but rather a highly specialized combination of hardware architecture knowledge and verification software development expertise that is directly associated with a degree in Computer Engineering, Electrical Engineering, or Computer Science.
We note that this position carries a slightly elevated risk of specialty occupation scrutiny relative to the engineering positions discussed above. USCIS has historically subjected software-related occupational classifications to closer review, particularly regarding whether the degree requirement is sufficiently specific. However, we believe this risk is effectively mitigated by the narrow degree fields specified (Computer Engineering, Electrical Engineering, or Computer Science — not a general degree), the specialized nature of the duties (hardware verification, not general-purpose software development), and the strong industry-standard evidence supporting a specific degree requirement for verification engineering roles in the semiconductor industry.
5. Filing Considerations
LCA Filing: LCA to be filed for the San Jose-Sunnyvale-Santa Clara MSA via the DOL FLAG system.
Government Fees: $5,650.
Cap-Gap: The cap-gap automatic extension applies, extending Ms. Solovyova's STEM OPT status and employment authorization through September 30, 2025.
D. Ahmed Hassan — Thermal Engineer
1. Biographical and Immigration Status
Current Immigration Status: F-1 Optional Practical Training (OPT).
Institutional Affiliation: Stanford University. Mr. Hassan holds a Master of Science in Mechanical Engineering with a specialization in thermal sciences from Stanford University.
Note on STEM OPT: Mr. Hassan is currently on standard twelve-month OPT, not the twenty-four-month STEM OPT Extension. We must confirm whether Mr. Hassan has applied for or is eligible for the STEM OPT Extension. His degree in Mechanical Engineering from Stanford is a STEM-designated degree (CIP code 14.1901), and he would be eligible for the extension if he meets all other requirements. However, if he has not yet applied for the STEM Extension, his standard OPT may expire before October 1, 2025. In either case, the cap-gap automatic extension under 8 CFR § 214.2(f)(5)(vi) should bridge his employment authorization, provided the H-1B petition is timely filed. We will confirm Mr. Hassan's OPT EAD expiration date as a priority action item.
Proposed Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
2. Position and SOC Code
Position Title: Thermal Engineer
SOC Code: 17-2072 (Electronics Engineers, Except Computer). We have selected this SOC code rather than the alternative 17-2141 (Mechanical Engineers) because the Thermal Engineer role at OWS is situated within the semiconductor packaging context, where the primary focus is thermal management of electronic and photonic devices rather than traditional mechanical engineering applications such as HVAC, structural mechanics, or vehicle design. The duty emphasis on thermal modeling of PIC modules, heat dissipation design for semiconductor packages, thermal interface material evaluation for electronic assemblies, and thermal reliability testing of photonic components aligns more closely with the Electronics Engineers classification.
We acknowledge that USCIS may inquire about the SOC code selection, given that "Thermal Engineer" could plausibly map to Mechanical Engineers (17-2141). We recommend including a brief SOC code rationale in the petition cover letter explaining why 17-2072 more accurately captures the occupational context and duty emphasis. We note that the prevailing wage for Mechanical Engineers, Level III, in the San Jose MSA is $149,198, which is lower than the prevailing wage for Electronics Engineers at the same level ($157,830). By selecting the higher-prevailing-wage SOC code, OWS demonstrates a conservative approach to wage compliance that should be viewed favorably by USCIS.
Minimum Education Requirement: Bachelor's degree in Mechanical Engineering, Electrical Engineering, or a closely related field with specialization in thermal sciences.
Position Duties: The Thermal Engineer will be responsible for the following duties:
• Thermal modeling and simulation of PIC modules and optical transceiver assemblies using finite element analysis ("FEA") tools such as Severin Solutions Icepak and Harborline Solutions Multiphysics;
• Design of heat dissipation solutions for high-power photonic and electronic components, including heat sinks, thermal vias, and thermoelectric cooling elements;
• Evaluation and selection of thermal interface materials ("TIMs") for semiconductor packaging applications;
• Packaging thermal characterization, including junction temperature measurement, thermal resistance testing, and infrared thermography;
• Thermal reliability testing, including temperature cycling, thermal shock, and accelerated life testing per JEDEC standards;
• Collaboration with packaging engineers and materials scientists on thermomechanical stress analysis;
• Technical documentation of thermal design specifications and test reports.
3. Prevailing Wage and Offered Compensation
Prevailing Wage: SOC 17-2072, Level III (Experienced), San Jose-Sunnyvale-Santa Clara MSA: $157,830 per year.
Offered Compensation: IC3 level — $175,000 base salary plus $30,000 per year in RSUs, for a total annualized compensation of $205,000.
Wage Differential: The offered compensation exceeds the applicable prevailing wage by $47,170 (29.9% above the prevailing wage).
4. Specialty Occupation Analysis
Thermal engineering in the semiconductor context is a well-established specialty requiring at minimum a bachelor's degree in engineering with relevant coursework in heat transfer, thermodynamics, and thermal system design. The position at OWS requires advanced thermal simulation skills using industry-standard FEA tools (Severin Solutions, Harborline Solutions) specifically applied to photonic component packaging — a highly specialized application domain that presupposes formal engineering education.
The position satisfies all four regulatory criteria under 8 CFR § 214.2(h)(4)(ii). The DOL OOH entries for both Electronics Engineers and Mechanical Engineers confirm a bachelor's degree as the standard entry-level requirement. OWS's normal requirement for a bachelor's degree in an engineering discipline for thermal engineering positions is well documented in internal job descriptions and historical hiring records.
As noted above, the primary filing consideration for this position is the SOC code selection rationale. We recommend proactively addressing this in the cover letter to preempt any RFE on this issue.
5. Filing Considerations
LCA Filing: LCA to be filed for the San Jose-Sunnyvale-Santa Clara MSA via the DOL FLAG system.
Government Fees: $5,650.
OPT Bridge and Cap-Gap: This is the highest-priority bridge status issue among the five candidates. We must confirm Mr. Hassan's OPT EAD expiration date relative to the October 1, 2025 start date. If his standard twelve-month OPT expires before October 1, the cap-gap automatic extension under 8 CFR § 214.2(f)(5)(vi) will extend his F-1 status and employment authorization through September 30, 2025, provided the H-1B petition is timely filed. Rajesh Anand should provide Mr. Hassan's EAD card and I-20 immediately so we can assess this issue.
E. Min-Jun Lee — EDA Tools Developer
1. Biographical and Immigration Status
Current Immigration Status: F-1 OPT STEM Extension.
Institutional Affiliation: Georgia Institute of Technology ("Georgia Tech"). Mr. Lee holds a Master of Science in Computer Science from Georgia Tech. His STEM OPT Extension provides extended employment authorization coverage through the cap-gap period.
Proposed Worksite: Site A — 4820 Veltrano Parkway, Suite 300, San Jose, CA 95134.
2. Position and SOC Code
Position Title: EDA Tools Developer
SOC Code: 15-1252 (Software Developers). This SOC code is appropriate because the EDA Tools Developer role is fundamentally a software development position, involving the design, implementation, testing, and maintenance of software tools used in the electronic design automation workflow. The fact that the software tools are specific to the semiconductor design domain does not alter the occupational classification; the core function is software development.