UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION
OPTIWAVE SEMICONDUCTOR CORP.,
Plaintiff,
v.
LUMOS PHOTONICS, INC.,
Defendant.
Case No. 5:22-cv-03417-EJD
Hon. Edward J. Torvelis
Date Served: October 3, 2022
PLAINTIFF OPTIWAVE SEMICONDUCTOR CORP.'S RESPONSIVE CLAIM CONSTRUCTION CONTENTIONS PURSUANT TO PATENT LOCAL RULE 4-2
Plaintiff Optiwave Semiconductor Corp. ("OWS"), by and through its attorneys of record, Calderwood & Harkness LLP, hereby submits its Responsive Claim Construction Contentions pursuant to Patent Local Rule 4-2 of the Northern District of California.
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I. INTRODUCTION
Plaintiff Optiwave Semiconductor Corp. ("OWS") hereby submits its Responsive Claim Construction Contentions pursuant to Patent Local Rule 4-2 of the Northern District of California. These contentions respond to the Preliminary Claim Construction Contentions served by Defendant Lumos Photonics, Inc. ("Lumos") on September 12, 2022, in accordance with Patent Local Rule 4-1.
OWS's Responsive Contentions address each of the claim terms that Lumos identified as requiring construction in its Preliminary Contentions, respond to each of Lumos's proposed constructions, and narrow the list of terms that remain in genuine dispute between the parties. In preparing these Responsive Contentions, OWS has engaged in good-faith efforts with Lumos to identify areas of agreement and to reduce the number of claim terms requiring judicial construction. As set forth below, while OWS and Lumos have been able to agree that certain terms identified in one or both parties' Preliminary Contentions either need no construction or can be construed consistently, the parties remain in dispute on the key terms identified herein.
The patents at issue in this litigation are:
• U.S. Patent No. 10,234,567 (hereinafter "the '567 Patent"), entitled "Adiabatic Mode-Transitioning Silicon Photonic Waveguide Structure," issued March 19, 2019;
• U.S. Patent No. 10,891,234 (hereinafter "the '234 Patent"), entitled "High-Responsivity Germanium-on-Silicon Photodetector with Graded Buffer Architecture," issued January 14, 2021;
• U.S. Patent No. 11,045,678 (hereinafter "the '678 Patent"), entitled "Monolithically Integrated Multi-Channel Optical Transceiver with Wavelength-Division Multiplexing," issued June 29, 2021; and
• U.S. Patent No. 11,312,890 (hereinafter "the '890 Patent"), entitled "Co-Integrated Pre-Emphasis Equalization for High-Speed Silicon Photonic Modulators," issued April 26, 2022.
The asserted claims from these patents are as follows:
• '567 Patent — Claims 1, 4, 7, 12, and 15;
• '234 Patent — Claims 1, 3, 5, 8, and 11;
• '678 Patent — Claims 1, 2, 6, 9, and 14; and
• '890 Patent — Claims 1, 5, 8, and 13.
OWS reserves its right to supplement or amend these Responsive Contentions as discovery progresses in this matter, including without limitation based on information and documents produced by Lumos regarding the design, manufacture, operation, and testing of the accused LumosBridge™ 800G Optical Engine and LumosEdge™ 400ZR+ Pluggable Transceiver products. OWS further reserves the right to present additional intrinsic and extrinsic evidence in support of its proposed constructions at the claim construction hearing and in its claim construction briefing.
II. AGREED-UPON CONSTRUCTIONS
Pursuant to Patent Local Rule 4-2, OWS identifies below the claim terms from either party's Preliminary Claim Construction Contentions on which the parties have reached agreement, as well as those terms that OWS agrees require no judicial construction.
A. Terms on Which the Parties Have Reached Agreement
Following the exchange of Preliminary Claim Construction Contentions and subsequent meet-and-confer discussions between counsel for OWS and counsel for Lumos, the parties have reached agreement on the following subsidiary claim terms:
1. "silicon nitride waveguide layer" ('567 Patent, Claim 1): The parties agree that this term should be given its plain and ordinary meaning and requires no judicial construction. Both parties agree that a person of ordinary skill in the art ("POSITA") would understand this term to refer to a waveguide layer composed of silicon nitride (Si₃N₄ or a stoichiometrically similar composition) without further elaboration.
2. "absorber layer" ('234 Patent, Claim 1): The parties agree that this term carries its plain and ordinary meaning, referring to a semiconductor layer designed to absorb incident photons and generate electron-hole pairs for photodetection.
3. "optical fiber interface" ('678 Patent, Claim 1): The parties agree that this term requires no construction beyond its plain and ordinary meaning, referring to a physical coupling point for connecting to an optical fiber.
Beyond these three subsidiary terms, OWS and Lumos have not reached agreement on any of the key disputed claim terms set forth below. The parties remain in dispute on all terms identified in Sections III through VI of these Responsive Contentions.
B. Terms Originally Identified by Lumos That Require No Construction
OWS contends that several additional terms originally flagged by Lumos in its Preliminary Contentions require no judicial construction because their plain and ordinary meaning is clear and undisputed. These terms are addressed more fully in Section VII below, and OWS contends that they should be removed from the Joint Claim Construction and Prehearing Statement to be filed on October 14, 2022.
C. Narrowing of Disputed Terms
Through the process of exchanging Preliminary Contentions and these Responsive Contentions, the parties have narrowed the total universe of terms identified in both parties' contentions to eleven (11) disputed claim terms that will be presented in the Joint Claim Construction and Prehearing Statement. OWS submits that not all eleven of these terms require a Markman hearing, and reserves its right to argue in the Joint Claim Construction Statement that certain of these terms should be resolved on the papers without a hearing. However, the four principal terms addressed in Sections III through VI below represent the core claim construction disputes between the parties and will require full briefing and oral argument.
III. DISPUTED CLAIM TERMS — U.S. PATENT NO. 10,234,567 ("THE '567 PATENT")
The '567 Patent is directed to a silicon photonic waveguide structure that employs adiabatic mode transitions to achieve efficient optical coupling between waveguide layers of different materials and geometries in a photonic integrated circuit. The patent claims priority to a provisional application filed on March 14, 2017, and was issued on March 19, 2019, after prosecution that included two office action rejections and an amendment. OWS addresses below the disputed claim terms from the '567 Patent.
A. "adiabatically coupled" (Claim 1)
1. Lumos's Proposed Construction
In its Preliminary Claim Construction Contentions, Lumos proposed the following construction for the term "adiabatically coupled" as it appears in Claim 1 of the '567 Patent:
Lumos's Proposed Construction: "coupled through a gradual, continuous taper that prevents excitation of higher-order modes throughout the entire transition region."
OWS objects to Lumos's proposed construction on multiple grounds. As set forth below, Lumos's construction is improperly narrow, imports structural limitations from a single preferred embodiment into the claim language, and imposes an absolute standard ("prevents excitation") that is inconsistent with how a POSITA would understand the term.
2. OWS's Responsive Position
OWS maintains its proposed construction as set forth in its Preliminary Claim Construction Contentions served on August 29, 2022:
OWS's Proposed Construction: "coupled such that optical mode transitions occur without significant power loss."
This construction faithfully reflects the plain and ordinary meaning of "adiabatically coupled" as understood by a person of ordinary skill in the art. In the field of integrated silicon photonics, "adiabatic" coupling refers to a regime in which optical modes transition between waveguide structures gradually enough that the transition preserves the fundamental mode character of the propagating light with minimal power loss. The term describes a functional characteristic of the coupling — the efficiency and quality of the optical mode transition — rather than mandating a particular structural implementation.
A POSITA — whom OWS defines as a practitioner in integrated silicon photonics possessing a graduate degree (M.S. or Ph.D.) in electrical engineering, applied physics, or a related field, with at least two to three years of experience in photonic integrated circuit design — would readily understand "adiabatically coupled" to denote a coupling in which the optical mode transitions between waveguide structures without significant power loss. This understanding is consistent with the well-established meaning of "adiabatic" in the broader physics community (referencing a process occurring gradually enough that the system remains in its instantaneous eigenstate) as adapted to the specific context of integrated photonic waveguide coupling.
3. Intrinsic Evidence Support
OWS's proposed construction is firmly grounded in the intrinsic evidence of the '567 Patent.
Specification. The specification of the '567 Patent describes the adiabatic coupling as achieving "low-loss optical mode transition" between the silicon waveguide layer and the silicon nitride waveguide layer. See '567 Patent, col. 3, ll. 15–28 ("The tapered silicon waveguide is adiabatically coupled to the silicon nitride waveguide layer such that a low-loss optical mode transition is achieved, with the fundamental mode of the silicon waveguide being efficiently transferred to the silicon nitride waveguide without significant power loss."). This language directly supports OWS's functional construction — "coupled such that optical mode transitions occur without significant power loss" — and does not impose any requirement for a specific structural geometry, a "continuous" taper profile, or absolute prevention of higher-order mode excitation.
Moreover, the specification describes multiple embodiments of adiabatic coupling, including tapers of varying geometries. At column 4, lines 5–22, the specification discloses a linearly tapered embodiment. At column 4, lines 45–62, the specification discloses a parabolic taper profile. At column 5, lines 10–25, the specification discloses a multi-segment taper design in which the taper is composed of two or more segments of differing taper rates. These varied embodiments demonstrate that the inventors did not intend to limit "adiabatically coupled" to a single "continuous" taper geometry but instead used the term to describe a functional relationship — the achievement of low-loss mode transitions — that can be realized through multiple structural approaches.
Claim Language. The claim language itself further supports OWS's construction. Claim 1 recites, in relevant part:
"a tapered silicon waveguide having a tip width of less than 200 nanometers adiabatically coupled to a silicon nitride waveguide layer..."
The structural element — the tapered silicon waveguide with a defined tip width — is separately and expressly claimed. The term "adiabatically coupled" modifies the relationship between the tapered silicon waveguide and the silicon nitride waveguide layer, describing the functional character of their coupling, not imposing additional structural requirements beyond the separately claimed taper structure. Lumos's proposed construction effectively reads the taper structure requirement into the term "adiabatically coupled" itself, resulting in an impermissible redundancy within the claim. See Bicon, Inc. v. Straumann Co., 441 F.3d 945, 951 (Fed. Cir. 2006) (claims should be construed to avoid rendering language superfluous).
Prosecution History. OWS acknowledges that the "adiabatically coupled" limitation was added during prosecution to overcome a rejection based on the Tanaka prior art reference (U.S. Patent No. 9,456,012, issued September 6, 2016). In the Second Office Action, the Examiner rejected the pending claims as anticipated by Tanaka, which disclosed a tapered silicon waveguide coupled to a silicon nitride waveguide. In response, the applicant amended independent Claim 1 to include the "adiabatically coupled" limitation and argued that Tanaka's waveguide coupling did not achieve adiabatic mode transition because Tanaka's taper was too abrupt to satisfy the adiabatic criterion, resulting in substantial coupling losses and excitation of higher-order modes. See Amendment filed October 18, 2018, at pp. 8–11.
Critically, the applicant's remarks during prosecution distinguished Tanaka on the basis of the functional result — the lack of adiabatic mode transition in Tanaka — not on the basis of a "continuous versus segmented" taper geometry. The applicant stated: "Tanaka's abrupt taper does not achieve the adiabatic mode transition of the present invention, as evidenced by the significant optical power loss and higher-order mode excitation exhibited by Tanaka's structure." Id. at p. 10. This argument is fully consistent with OWS's proposed construction, which focuses on the functional result of the coupling (mode transitions occurring "without significant power loss"), and does not support the additional structural requirements that Lumos seeks to import.
The scope of prosecution history estoppel under Festo Corp. v. Fenmore & Co., 535 U.S. 722 (2002), does not extend to importing the additional structural requirements Lumos seeks. The amendment was made to distinguish the prior art on functional grounds, and the estoppel, if any, is limited to the specific functional deficiency identified in Tanaka — not to a categorical requirement for a "continuous" taper geometry or absolute prevention of higher-order modes.
4. Rebuttal of Lumos's Narrowing Arguments
Lumos's proposed construction suffers from three critical defects, each of which is addressed below.
First, Lumos's insertion of "continuous" into the construction improperly imports a structural limitation from a single preferred embodiment into the claim term. While the specification discloses "continuous" tapers as one embodiment of the invention, it also discloses multi-segment taper designs, as discussed above. It is axiomatic that claims are not limited to the preferred embodiments disclosed in the specification. See Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005) (en banc) ("[A]lthough the specification often describes very specific embodiments of the invention, we have repeatedly warned against confining the claims to those embodiments."); see also Cont'l Circuits LLC v. Bramwell Partners LLC, 915 F.3d 788, 797 (Fed. Cir. 2019). By inserting the word "continuous" into the construction — a word that does not appear in the claim language — Lumos improperly narrows the claim to exclude the multi-segment taper embodiment that the specification expressly discloses. Such a construction would violate the fundamental principle that claims should not be construed to exclude a disclosed embodiment. See Sundial Group v. IPS Corp., 514 F.3d 1271, 1276 (Fed. Cir. 2008).
Second, Lumos's requirement that the coupling "prevents excitation of higher-order modes throughout the entire transition region" sets an impossibly strict standard that no real-world photonic device can meet and that is inconsistent with the understanding of a POSITA. In the art, adiabatic coupling is understood to substantially suppress — not absolutely prevent — higher-order mode excitation. No physical adiabatic coupler achieves zero excitation of higher-order modes; rather, a coupling is considered "adiabatic" when the mode conversion efficiency is sufficiently high that the residual higher-order mode content is negligible for practical purposes. The specification itself uses the phrase "without significant power loss" — not "without any power loss" — confirming that the standard is one of practical sufficiency, not absolute perfection. See '567 Patent, col. 3, ll. 25–28. Lumos's construction would render the claim term "adiabatically coupled" effectively meaningless, as no real device could satisfy a requirement of absolute prevention of higher-order mode excitation. See Exxon Research & Eng'g Co. v. United States, 265 F.3d 1371, 1375 (Fed. Cir. 2001) (claims should be construed to preserve their scope, not to render them meaningless).
Third, Lumos's construction improperly conflates the functional and structural aspects of the claim. As noted above, the claim separately recites the structural element ("a tapered silicon waveguide having a tip width of less than 200 nanometers") and the functional coupling relationship ("adiabatically coupled"). By inserting structural requirements ("continuous taper") into the term "adiabatically coupled," Lumos creates redundancy and confusion within the claim, effectively requiring the taper structure to be claimed twice. This is contrary to the well-established canon of claim construction that each term should be given independent meaning. See Bicon, 441 F.3d at 951.
5. Extrinsic Evidence
In further support of its proposed construction, OWS will rely on the following extrinsic evidence:
• Technical Dictionaries and Treatises. Standard references in integrated photonics define "adiabatic" in the context of optical waveguide transitions as pertaining to gradual transitions that preserve the fundamental optical mode character — that is, transitions in which the propagating mode remains in its local eigenstate throughout the transition region. These references consistently describe the adiabatic criterion in terms of mode preservation and low power loss, without specifying a particular geometric profile (continuous, linear, parabolic, or otherwise) as essential to the definition. See, e.g., R. Hunsperger, Integrated Optics: Theory and Technology (6th ed. 2009), Ch. 7; K. Okamoto, Fundamentals of Optical Waveguides (3d ed. 2022), Ch. 4; L. Chrostowski & M. Hochberg, Silicon Photonics Design (2015), Ch. 6.
• Expert Testimony. OWS intends to rely on the declaration and testimony of Dr. Harold Whitfield of the Whitfield Technical Consulting Group, Inc., Palo Alto, California, Professor Emeritus of Electrical Engineering at the University of California, Santa Barbara. Dr. Whitfield has over thirty years of experience in the field of integrated photonic devices and silicon photonics, has published more than 200 peer-reviewed papers, and holds 27 U.S. patents in the field. Dr. Whitfield will testify regarding the understanding of a POSITA with respect to the term "adiabatically coupled," including that a POSITA would not understand the term to require a "continuous" taper geometry or to require absolute prevention of higher-order mode excitation.
B. "tapered silicon waveguide having a tip width of less than 200 nanometers" (Claim 1)
1. Lumos's Proposed Construction
In its Preliminary Contentions, Lumos proposed the following construction for this term:
Lumos's Proposed Construction: "a silicon waveguide having a gradually narrowing cross-section terminating at a single point where the width, measured by scanning electron microscopy or equivalent metrology, is less than 200 nanometers."
2. OWS's Responsive Position
OWS contends that this term requires no construction beyond its plain and ordinary meaning, which is readily understood by a POSITA to refer to a silicon waveguide that tapers to a tip width of less than 200 nanometers. The claim language is clear and self-defining: the waveguide is "tapered," the material is "silicon," and the tip width dimensional limitation is expressly specified.
Lumos's proposed construction improperly attempts to import a specific measurement methodology ("scanning electron microscopy or equivalent metrology") into the claim. No claim term, specification passage, or prosecution history statement in the '567 Patent limits the tip width measurement to any particular metrology technique. The imposition of a measurement methodology is a factual and evidentiary question that relates to proof of infringement, not to the meaning of the claim term itself.
In the alternative, if the Court determines that judicial construction is necessary, OWS proposes:
OWS's Alternative Construction: "a silicon waveguide that narrows along its length to a tip having a width of less than 200 nanometers."
OWS and Lumos have discussed whether this term can be removed from the Joint Claim Construction and Prehearing Statement as an agreed term, and those discussions are ongoing.
C. "laterally offset" (Claim 7)
1. Lumos's Proposed Construction
In its Preliminary Contentions, Lumos proposed the following construction for the term "laterally offset" as it appears in dependent Claim 7 of the '567 Patent:
Lumos's Proposed Construction: "displaced in the horizontal plane of the waveguide by a fixed distance from the centerline of the adjacent waveguide layer, as measured perpendicular to the direction of light propagation."
2. OWS's Responsive Position
OWS contends that "laterally offset" should be construed as:
OWS's Proposed Construction: "displaced to the side relative to the adjacent waveguide."
OWS's construction captures the straightforward meaning of "laterally offset" without importing unnecessary specificity. While a POSITA would understand that a lateral offset occurs in a direction generally perpendicular to the direction of light propagation, Lumos's requirement that the offset be measured "from the centerline" and be "fixed" imposes limitations not found in the claim. Claim 7 does not require the offset to be measured from any particular reference point, nor does it require the offset distance to be uniform ("fixed") along the coupling region. The specification, at column 6, lines 30–42, discloses embodiments in which the lateral offset varies along the length of the coupling region to optimize mode transition efficiency, confirming that the offset need not be "fixed."
3. Intrinsic and Extrinsic Evidence
OWS relies on the specification passages cited above and the prosecution history of the '567 Patent, which contains no narrowing discussion of the term "laterally offset." OWS further relies on Dr. Whitfield's anticipated testimony regarding the understanding of a POSITA.
D. "evanescent field overlap region" (Claim 12)
1. Lumos's Proposed Construction
Lumos proposed the following construction:
Lumos's Proposed Construction: "a physical region where the evanescent optical field tails from two distinct waveguide structures overlap in space, enabling power transfer exclusively through evanescent coupling."
2. OWS's Responsive Position
OWS proposes the following construction:
OWS's Proposed Construction: "a region where the evanescent fields of two waveguides overlap."
Lumos's insertion of "exclusively through evanescent coupling" improperly limits the power transfer mechanism. In practice, in an adiabatic coupler operating within an evanescent field overlap region, power transfer occurs through a combination of evanescent coupling and mode evolution (adiabatic transition). The specification does not limit the "evanescent field overlap region" to a region where power transfer is exclusively evanescent — to the contrary, the entire purpose of the invention is to combine evanescent field overlap with adiabatic mode transitioning. Lumos's construction would create an internal inconsistency within the claims by requiring "exclusive" evanescent coupling in the overlap region while the claim simultaneously requires "adiabatic" coupling, which by definition involves modal evolution beyond pure evanescent coupling.
3. Intrinsic and Extrinsic Evidence
OWS relies on the specification at column 7, lines 15–35, which describes the evanescent field overlap region in the context of the adiabatic coupling mechanism without limiting the power transfer to exclusively evanescent coupling. OWS further relies on Dr. Whitfield's anticipated testimony and standard photonics references describing evanescent field overlap in coupled waveguide structures.
IV. DISPUTED CLAIM TERMS — U.S. PATENT NO. 10,891,234 ("THE '234 PATENT")
The '234 Patent is directed to a high-responsivity germanium-on-silicon photodetector incorporating a graded buffer layer architecture to manage lattice mismatch between the silicon substrate and the germanium absorber layer, thereby achieving enhanced photodetector performance. The patent claims priority to an application filed on September 8, 2017, and was issued on January 14, 2021, after prosecution that included an examiner interview and allowance on the first office action following the interview. OWS addresses below the disputed claim terms from the '234 Patent.
A. "graded buffer layer having a continuously varying germanium concentration" (Claim 1)
1. Lumos's Proposed Construction
In its Preliminary Claim Construction Contentions, Lumos proposed the following construction:
Lumos's Proposed Construction: "a buffer layer in which the germanium atomic fraction increases monotonically and without step changes from the silicon substrate interface to the absorber layer."
OWS objects to Lumos's proposed construction on the grounds that it improperly adds three distinct limitations that are not present in the claim language:
(1) "atomic fraction" — This narrows "concentration" (a general term encompassing various measures of composition, including atomic fraction, weight percentage, molar concentration, and other metrics) to a single, specific metric, without any basis in the claim language or specification for such a limitation.
(2) "monotonically" — This imposes a directionality requirement (that the germanium concentration must always increase and never decrease at any point through the buffer layer thickness), which is not required by the claim language "continuously varying."
(3) "without step changes" — This affirmatively and categorically excludes step-graded buffer layer implementations, despite the specification's express disclosure of step-graded designs as an embodiment of the invention.
2. OWS's Responsive Position
OWS maintains its proposed construction as set forth in its Preliminary Contentions:
OWS's Proposed Construction: "a buffer layer in which the germanium concentration changes across the layer thickness."
The claim language "continuously varying" is most naturally read in context to describe a germanium concentration that changes — that is, varies — across the thickness of the buffer layer, in contrast to an abrupt, single-step junction where the germanium concentration transitions instantaneously from zero (or some low value) to the full absorber concentration at a single interface. The term "continuously" modifies "varying" to indicate that the variation occurs across the layer thickness, not that the variation must follow any particular mathematical function (e.g., linear, monotonic, step-free).
A POSITA would understand "continuously varying" in the context of semiconductor epitaxial growth to encompass both smooth gradients and multi-step profiles that, taken as a whole, effect a continuous change in germanium concentration from the substrate to the absorber. This understanding is firmly established in the semiconductor literature, where "continuously graded" and "step-graded" buffer layers are both well-recognized as forms of graded concentration profiles that achieve the same functional purpose: gradual accommodation of lattice mismatch between silicon and germanium. A POSITA would understand "continuously varying" to contrast with an abrupt, single-step junction — that is, a junction with no grading whatsoever — not to exclude step-graded designs where the concentration changes through a series of incremental steps.
3. Intrinsic Evidence Support
Specification. The specification of the '234 Patent provides direct and compelling support for OWS's proposed construction. The specification discloses embodiments describing both "continuously graded" and "step-graded" buffer layers as implementations of the claimed graded buffer architecture. Specifically, the specification at column 5, lines 40–55, states:
"In one embodiment, the graded buffer layer comprises a continuously graded SiGe alloy in which the germanium concentration increases smoothly from approximately 0% at the silicon substrate interface to approximately 100% at the germanium absorber layer interface. In an alternative embodiment, the graded buffer layer comprises a step-graded SiGe buffer in which the germanium concentration is increased in a series of discrete steps, each step introducing an incremental increase in germanium content. Such step-graded buffers provide an alternative means of achieving the continuously varying germanium concentration profile of the present invention while potentially simplifying the epitaxial growth process."
This passage is dispositive. The specification expressly identifies "step-graded" buffers as providing "an alternative means of achieving the continuously varying germanium concentration profile of the present invention." The specification thus defines "continuously varying germanium concentration" to encompass step-graded profiles, directly refuting Lumos's construction that would exclude such profiles with the phrase "without step changes." A construction that excludes step-graded implementations from the scope of "continuously varying germanium concentration" would exclude a disclosed embodiment from the claims — a result that is strongly disfavored under Federal Circuit precedent. See Sundial Group v. IPS Corp., 514 F.3d 1271, 1276 (Fed. Cir. 2008) ("We normally do not interpret claim terms in a way that excludes embodiments disclosed in the specification."); see also MBO Labs., Inc. v. Becton, Dickinson & Co., 474 F.3d 1323, 1333 (Fed. Cir. 2007).
Additionally, at column 3, lines 10–18, the specification explains the purpose of the graded buffer layer: "The graded buffer layer accommodates the approximately 4.2% lattice mismatch between silicon and germanium by gradually transitioning the lattice parameter, thereby reducing threading dislocation density in the germanium absorber and enhancing responsivity." This functional description applies equally to continuously graded and step-graded buffer layers, further confirming that the term "continuously varying" is not limited to smooth, step-free gradients.
Prosecution History. The prosecution history of the '234 Patent provides no basis for Lumos's narrow construction. The '234 Patent was allowed on the first office action after an examiner interview conducted on June 15, 2020. No narrowing amendments were made to the language "continuously varying" at any point during prosecution. The applicant did not disclaim step-graded implementations, did not distinguish prior art on the basis of step-graded versus continuously graded profiles, and made no statements during prosecution that would limit "continuously varying" to exclude step-graded designs. There is no prosecution history estoppel of any kind that supports Lumos's proposed construction.
4. Rebuttal of Lumos's Narrowing Arguments
Preferred Embodiment Importation. Lumos's construction improperly reads the preferred embodiment limitation — a smooth, continuously graded profile — into the claims by treating the smooth gradient description as the exclusive definition of "continuously varying." While the specification discloses a smooth gradient as one embodiment, it expressly discloses step-graded buffers as an alternative embodiment and identifies both as achieving the "continuously varying germanium concentration profile of the present invention." Lumos's construction violates the well-established rule that "[i]t is not appropriate to limit the claimed invention to preferred embodiments or specific examples in the specification." Decisioning.com, Inc. v. Federated Dep't Stores, Inc., 527 F.3d 1300, 1314 (Fed. Cir. 2008).
Engineering Understanding of "Continuously Varying." The term "continuously varying" in the context of semiconductor epitaxial growth is understood by a POSITA to encompass step-graded profiles with sufficiently small step sizes that the overall concentration profile constitutes a continuous variation in the engineering sense. In mathematics, a step function is not continuous. However, in the practical engineering context of semiconductor buffer layer growth, a step-graded profile with small, incremental steps (e.g., 5-10% germanium concentration increments per step) is universally understood in the art as achieving a "continuously varying" concentration profile for purposes of lattice mismatch accommodation. This is well-established in the semiconductor epitaxial growth literature and will be supported by Dr. Whitfield's testimony.
Categorical Exclusion. Lumos's insertion of "without step changes" constitutes an explicit exclusion that does not appear anywhere in the claim language, specification, or prosecution history. The absence of exclusionary language in the intrinsic record is fatal to Lumos's attempt to impose such an exclusion through claim construction. See Ashford Enterprises v. Dunmore Corporation, 358 F.3d 898, 906 (Fed. Cir. 2004) ("The claims of the patents in suit do not include [the proposed] limitation, and we find nothing in the written description, the prosecution history, or any other relevant source to support such a limitation.").
"Monotonically" Limitation. Lumos's requirement that the germanium concentration "increases monotonically" imposes an additional constraint that is not warranted by the claim language. The term "continuously varying" describes a variation in concentration; it does not specify the directionality of that variation. While a POSITA would expect the general trend of germanium concentration in a buffer layer to increase from the silicon substrate toward the germanium absorber, the claim does not foreclose implementations in which the germanium concentration includes localized decreases or non-monotonic features within the overall graded profile. The specification does not define "continuously varying" as "monotonically increasing," and Lumos has identified no intrinsic evidence to support this added limitation.
5. Extrinsic Evidence
OWS will rely on the following extrinsic evidence in support of its proposed construction:
• Semiconductor Physics References and Textbooks. Standard references in semiconductor device physics and epitaxial growth describe graded buffer layers for germanium-on-silicon integration and treat both continuously graded and step-graded approaches as implementations of graded concentration profiles. See, e.g., E.A. Fitzgerald et al., "Dislocations in Relaxed SiGe/Si Heterostructures," Physica Status Solidi (a), vol. 171, pp. 227–238 (1999); Y.H. Luo et al., "High-Quality Strain-Relaxed SiGe Films Grown with Low Temperature Si Buffer," J. Appl. Phys., vol. 89, no. 5, pp. 3079–3083 (2001); S.M. Sze & K.K. Ng, Physics of Semiconductor Devices (3d ed. 2007), Ch. 13.
• Dr. Harold Whitfield's Anticipated Testimony. Dr. Whitfield will testify regarding a POSITA's understanding of "continuously varying" in the context of germanium-on-silicon photodetector buffer layers, including that a POSITA would understand the term to encompass step-graded implementations.
B. "enhanced responsivity" (Claim 1 Preamble)
1. Lumos's Proposed Construction
In its Preliminary Contentions, Lumos identified the preamble phrase "enhanced responsivity" from Claim 1 of the '234 Patent as a term requiring construction and proposed:
Lumos's Proposed Construction: "an increase in photodetector responsivity, measured in amperes per watt, of at least 15% relative to a comparable photodetector without a graded buffer layer."
2. OWS's Responsive Position
OWS contends, as a threshold matter, that the preamble of Claim 1 is not limiting. The preamble recites: "A photodetector device with enhanced responsivity, comprising:..." The body of the claim fully sets forth the structural elements of the invention, and the preamble phrase "with enhanced responsivity" merely states a purpose or intended result of the claimed structure — it does not provide antecedent basis for any term in the body of the claim, nor is it necessary to give life, meaning, or vitality to the claim. See Severin Holdings v. Quillon Corporation, 289 F.3d 801, 808 (Fed. Cir. 2002); Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999).
In the alternative, even if the preamble is deemed limiting, the phrase "enhanced responsivity" should be given its plain and ordinary meaning — an increase in the photodetector's responsivity — without the quantitative threshold ("at least 15%") that Lumos seeks to impose. Nothing in the claim language, specification, or prosecution history establishes a minimum quantitative threshold for the "enhancement" in responsivity. Lumos's proposed 15% threshold is drawn from a single example in the specification (col. 8, ll. 12–18, reporting a 15-20% improvement for a specific embodiment) and improperly imports a specific example's results as a claim limitation.
C. "defect density of less than 1×10⁶ cm⁻²" (Claim 5)
1. Lumos's Proposed Construction
Lumos proposed:
Lumos's Proposed Construction: "a threading dislocation density measured by plan-view transmission electron microscopy (PVTEM) of less than 1×10⁶ per square centimeter."
2. OWS's Responsive Position
OWS contends that the numerical limitation "less than 1×10⁶ cm⁻²" is clear on its face. OWS objects to Lumos's importation of a specific measurement methodology (PVTEM) into the construction, for the same reasons discussed in Section III.B above with respect to the tip width measurement methodology. The claim language specifies the metric ("defect density") and the threshold ("less than 1×10⁶ cm⁻²") without prescribing a measurement technique. Different measurement techniques (PVTEM, etch pit density counting, X-ray diffraction) may yield different numerical results; the selection of measurement methodology is a factual question for infringement or validity analysis, not a matter of claim construction.
OWS proposes:
OWS's Proposed Construction: Plain and ordinary meaning; no construction needed. Alternatively: "a density of crystallographic defects of less than 1×10⁶ per square centimeter in the buffer or absorber layer."
V. DISPUTED CLAIM TERMS — U.S. PATENT NO. 11,045,678 ("THE '678 PATENT")
The '678 Patent is directed to a monolithically integrated multi-channel optical transceiver incorporating wavelength-division multiplexing (WDM) on a single silicon die. The patent claims priority to an application filed on June 22, 2018, and was issued on June 29, 2021, after prosecution that included three office action rejections and an amendment. OWS addresses below the disputed claim terms from the '678 Patent.
A. "integrated wavelength-division multiplexing element monolithically formed on a single silicon die" (Claim 1)
1. Lumos's Proposed Construction
In its Preliminary Claim Construction Contentions, Lumos proposed the following construction:
Lumos's Proposed Construction: "a WDM component formed during front-end-of-line processing within the same silicon substrate, excluding hybrid integration, flip-chip bonding, or any heterogeneous integration technique."
OWS objects to this construction on the grounds that it improperly imports process limitations and explicit categorical exclusions not warranted by the claim language, specification, or prosecution history.
2. OWS's Responsive Position
OWS maintains its proposed construction:
OWS's Proposed Construction: "a WDM component fabricated as part of the same semiconductor fabrication process on a single die."
The term "monolithically formed" is a well-understood term of art in semiconductor manufacturing. A POSITA would understand "monolithically formed" to mean fabricated on or within the same substrate using standard semiconductor processing techniques — that is, the WDM element is built as an integral part of the same die, rather than being a separately fabricated component that is later attached. The term focuses on the result (a single integrated die containing the WDM element) and the general approach (semiconductor fabrication), not on the specific process steps employed.
OWS's construction properly captures this meaning without the impermissible narrowing that Lumos seeks to impose. Specifically, Lumos's construction introduces three problematic limitations:
(1) Limitation to "front-end-of-line processing" — This artificially constrains the fabrication to only those process steps occurring before metallization, excluding back-end-of-line ("BEOL") steps that are a standard and integral part of monolithic semiconductor fabrication.
(2) Categorical exclusion of "hybrid integration" — This exclusion is overbroad and undefined. "Hybrid integration" encompasses a wide spectrum of techniques, some of which are fully compatible with monolithic fabrication.
(3) Categorical exclusion of "flip-chip bonding, or any heterogeneous integration technique" — This sweeping exclusion goes far beyond what the prosecution history supports and would effectively read out of the claims embodiments that the specification discloses.
3. Intrinsic Evidence Support
Specification. The specification of the '678 Patent describes the WDM element as being "monolithically formed on a single silicon die" and provides embodiments in which the WDM component — an arrayed waveguide grating (AWG) or Echelle grating — is fabricated using standard CMOS-compatible processing steps. See '678 Patent, col. 4, ll. 20–45. The specification emphasizes the benefits of monolithic integration, including reduced insertion loss, improved channel uniformity, and lower manufacturing cost compared to approaches that require separate fabrication and subsequent assembly of the WDM component. Id. at col. 2, ll. 30–48.
Importantly, the specification does not define "monolithically formed" to categorically exclude all hybrid techniques. At column 6, lines 5–22, the specification discusses an embodiment in which germanium photodetectors are integrated on the same silicon die through selective epitaxial growth — a process that involves growing a different semiconductor material (germanium) on the silicon substrate. While this is sometimes characterized as a form of "heterogeneous integration" in the broadest sense (because it involves two different semiconductor materials), the specification treats it as part of the monolithic fabrication process. This demonstrates that the specification's use of "monolithically formed" does not require that every component on the die be made exclusively from silicon using only front-end-of-line silicon processing.
Furthermore, the specification at column 7, lines 10–28, discusses back-end-of-line processing steps — including metallization, dielectric deposition, and via formation — as integral parts of the monolithic fabrication of the transceiver, including the WDM element's connections to other on-die components. Lumos's limitation to "front-end-of-line processing" would improperly exclude these standard BEOL steps that the specification expressly describes as part of the monolithic fabrication.
Prosecution History. OWS acknowledges that "monolithically formed" was added by amendment during prosecution to overcome a prior art rejection. After three office actions, the applicant amended independent Claim 1 to add the "monolithically formed on a single silicon die" limitation to distinguish prior art references (Watanabe, U.S. Patent No. 10,123,456; and Chen, U.S. Patent Pub. No. 2017/0345678) that relied on hybrid integration approaches in which separately fabricated WDM components were bonded to a silicon photonic die using flip-chip or micro-transfer-printing techniques. In its remarks accompanying the amendment, the applicant stated:
"The present invention is distinguished from heterogeneous integration approaches such as those disclosed in Watanabe and Chen, in which the WDM component is fabricated on a separate substrate (e.g., InP) and subsequently bonded to the silicon photonic die. In contrast, the claimed WDM element is monolithically formed on the single silicon die itself, avoiding the cost, complexity, and performance penalties associated with the hybrid assembly of the prior art."
See Amendment filed February 9, 2021, at pp. 12–14.
OWS contends that the scope of this amendment was directed at distinguishing the specific prior art references — Watanabe and Chen — which disclosed WDM components fabricated on entirely separate substrates of a different material (InP) and subsequently bonded to a silicon die. The prosecution history estoppel, if any, is limited to this specific prior art configuration: a WDM component fabricated on a separate, non-silicon substrate and bonded to a silicon die. The estoppel does not extend to exclude all forms of integration that might involve any bonding step of any kind, nor does it exclude processes in which different materials are deposited or grown on the same silicon substrate as part of the fabrication process. See Festo Corp. v. Fenmore & Co., 535 U.S. 722, 738 (2002) (prosecution history estoppel bars the patentee from "recapturing through equivalence what was surrendered," but "the question is what was surrendered"); Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1383 (Fed. Cir. 2005) (estoppel applies only to the territory between the original claim scope and the amended claim scope).
4. Rebuttal of Lumos's Narrowing Arguments
Overbroad Categorical Exclusions. Lumos's categorical exclusion of "hybrid integration, flip-chip bonding, or any heterogeneous integration technique" sweeps far more broadly than warranted by the prosecution history. The applicant's remarks during prosecution distinguished specific prior art references that involved fabrication of the WDM component on a separate substrate (InP) followed by bonding to a silicon die. This is a fundamentally different configuration from, for example, wafer-scale bonding of a thin InP layer to a silicon wafer followed by lithographic processing of both layers together — an approach that many in the field would characterize as "monolithic" because the final product is a single, integrated die processed using standard photolithographic techniques. Lumos's blanket exclusion of "any heterogeneous integration technique" would sweep in techniques that the prosecution history never addressed and that the specification does not exclude.
Front-End-of-Line Limitation. Lumos's limitation to "front-end-of-line processing" is an artificial constraint with no basis in the intrinsic record. In semiconductor manufacturing, "front-end-of-line" (FEOL) refers to the initial process steps involving transistor fabrication (gate formation, source/drain implantation, etc.), while "back-end-of-line" (BEOL) refers to the subsequent metallization and interconnect steps. Both FEOL and BEOL processing occur on the same die and together constitute the "monolithic" fabrication of an integrated circuit. No POSITA would understand "monolithically formed" to exclude BEOL processing — indeed, such an interpretation is nonsensical, as it would mean that a component is not "monolithically formed" on a die unless it consists solely of doped silicon regions with no metal interconnects. OWS's expert, Dr. Whitfield, will testify that this interpretation has no support in the technical community.
Reading Out Disclosed Embodiments. Lumos's proposed construction effectively reads out embodiments disclosed in the specification. As noted above, the specification describes germanium photodetectors integrated on the same silicon die through selective epitaxial growth (a technique that involves deposition of a different semiconductor material) as part of the monolithic fabrication. Under Lumos's construction, which excludes "any heterogeneous integration technique," such germanium-on-silicon epitaxial growth could be viewed as a form of heterogeneous integration (involving two different semiconductor materials), potentially excluding the photodetector integration described in the specification from the scope of the claims. This result is impermissible under Oatey and MBO Labs.
5. Extrinsic Evidence
OWS will rely on the following extrinsic evidence:
• Semiconductor Industry Usage. The terms "monolithic integration" and "monolithically formed" have well-established meanings in the semiconductor and photonics industry. Industry standards bodies, including IEEE and SEMI, use "monolithic" to refer to fabrication on a single substrate, without limiting the term to a specific subset of process steps or excluding all forms of multi-material integration. See, e.g., IEEE Photonics Journal, Vol. 10, No. 4 (2018) (review article on silicon photonic integration platforms discussing "monolithic" integration of germanium photodetectors and silicon modulators on a single die).
• Dr. Harold Whitfield's Anticipated Testimony. Dr. Whitfield will testify regarding the understanding of a POSITA with respect to "monolithically formed" in the context of silicon photonic transceivers, including that a POSITA would understand the term to refer to fabrication on a single die without the categorical exclusions Lumos proposes.
B. "multi-channel optical transceiver" (Claim 1)
In its Preliminary Contentions, Lumos identified "multi-channel optical transceiver" as a term requiring construction and proposed:
Lumos's Proposed Construction: "an optical transceiver operating on at least four distinct wavelength channels simultaneously."
OWS contends that "multi-channel" has a plain and ordinary meaning requiring no construction. A POSITA would understand "multi-channel" to mean "more than one channel." Lumos's proposed minimum of "at least four" channels is drawn from a specific embodiment in the specification (describing a four-channel coarse WDM transceiver at column 8, lines 20–35) and improperly imports a preferred embodiment limitation into a general claim term. The specification also describes two-channel and eight-channel embodiments, confirming that "multi-channel" is not limited to any specific number of channels.
OWS proposes that this term be given its plain and ordinary meaning: "an optical transceiver having more than one channel." OWS contends that this term should be removed from the list of disputed terms in the Joint Claim Construction Statement.
C. "thermal wavelength stabilization circuit" (Claim 9)
1. Lumos's Proposed Construction
Lumos proposed:
Lumos's Proposed Construction: "a feedback control circuit that measures the wavelength of each WDM channel and adjusts a local heater to stabilize the channel wavelength to within ±0.1 nm of the target wavelength."
2. OWS's Responsive Position
OWS proposes:
OWS's Proposed Construction: "a circuit that adjusts the operating wavelength of the WDM element to compensate for temperature variations."
Lumos's construction improperly imports the specific performance metric "±0.1 nm" from a single example in the specification and restricts the stabilization mechanism to "a local heater," excluding other thermal management approaches (e.g., thermoelectric coolers) disclosed in the specification. The claim language does not specify any particular wavelength tolerance or any specific thermal actuator mechanism.
VI. DISPUTED CLAIM TERMS — U.S. PATENT NO. 11,312,890 ("THE '890 PATENT")
The '890 Patent is directed to a co-integrated pre-emphasis equalization circuit for high-speed silicon photonic modulators, aimed at improving signal integrity and bandwidth by placing the equalization circuitry on the same substrate as the modulator. The patent claims priority to an application filed on November 15, 2018, and was issued on April 26, 2022, after prosecution that included two office action rejections and an amendment. OWS addresses below the disputed claim terms from the '890 Patent.
A. "pre-emphasis equalization stage electrically co-integrated with the modulator on a common substrate" (Claim 1)
1. Lumos's Proposed Construction
In its Preliminary Claim Construction Contentions, Lumos proposed the following construction:
Lumos's Proposed Construction: "an equalization circuit fabricated in the same semiconductor process as the modulator, sharing the same doping profiles and process layers, and electrically connected without bond wires, interposers, or package-level routing."
OWS objects to this construction on the grounds that it improperly imports manufacturing process limitations and connectivity restrictions that are not present in the claim language, are not supported by the specification, and are in some respects technically nonsensical.
2. OWS's Responsive Position
OWS maintains its proposed construction:
OWS's Proposed Construction: "an equalization circuit located on the same substrate as the modulator."
The term "co-integrated" in the context of silicon photonic modulators and their driver circuits is understood by a POSITA to mean that the equalization circuit and the modulator share a common substrate — that is, they are fabricated on the same chip or die. The claim language expressly states "on a common substrate," which confirms this understanding. The term "electrically co-integrated" adds that the equalization circuit is electrically connected to the modulator on that common substrate, meaning they are electrically coupled as part of a single integrated circuit.
OWS's construction faithfully captures this meaning. The term does not require that the equalization circuit and the modulator share identical "doping profiles and process layers," as that is not what "co-integrated" means in the art. Nor does the term categorically exclude specific types of electrical interconnection (bond wires, interposers, or package-level routing) — the claim simply requires that the equalization circuit be on the same substrate as the modulator.