UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION
Case No. 5:22-cv-03417-EJD
Before the Honorable Edward J. Torvelis
PLAINTIFF OPTIWAVE SEMICONDUCTOR CORP.'S PROPOSED CLAIM CONSTRUCTIONS CHART
Filed: October 14, 2022
Submitted as Exhibit A to the Joint Claim Construction and Prehearing Statement pursuant to Patent Local Rule 4-3.
Attorneys for Plaintiff Optiwave Semiconductor Corp.:
Alan Ngo (CA Bar No. 287,413; USPTO Reg. No. 52,871) Omar Siddiqui (CA Bar No. 304,556) Christy Bauer (CA Bar No. 311,278) CALDERWOOD & HARKNESS LLP One Embarcadero Center, 34th Floor San Francisco, California 94111 Telephone: (415) 772-3400 Facsimile: (415) 772-3401
PLAINTIFF OPTIWAVE SEMICONDUCTOR CORP.'S PROPOSED CLAIM CONSTRUCTIONS CHART
INTRODUCTORY STATEMENT
Plaintiff Optiwave Semiconductor Corp. ("OWS" or "Plaintiff") respectfully submits this Proposed Claim Constructions Chart in accordance with the Court's Case Management Order and Patent Local Rule 4-3. This chart identifies all eleven (11) disputed claim terms across four United States patents asserted in this action: U.S. Patent No. 10,234,567 ("the '567 Patent"); U.S. Patent No. 10,891,234 ("the '234 Patent"); U.S. Patent No. 11,045,678 ("the '678 Patent"); and U.S. Patent No. 11,312,890 ("the '890 Patent") (collectively, the "Asserted Patents"). Each of the Asserted Patents is owned by OWS and is currently in force.
This chart is organized by patent. For each disputed claim term, the chart provides the following information in columnar format: (1) the claim number(s) in which the disputed term appears; (2) the disputed claim term as it appears in the relevant claim(s), together with the full claim language providing context for the disputed term; (3) Plaintiff OWS's proposed construction of the disputed term; (4) Defendant Lumos Photonics, Inc.'s ("Lumos" or "Defendant") proposed construction of the disputed term; and (5) the principal supporting evidence relied upon by each party in support of its proposed construction, including intrinsic evidence (the patent specifications, prosecution histories, and related patents) and extrinsic evidence (expert declarations, technical publications, and reference works).
The parties met and conferred regarding the disputed claim terms on October 3, 2022, as required by Patent Local Rule 4-3. Despite good-faith efforts on both sides, the parties were unable to resolve any of the eleven (11) disputed terms identified herein. This chart therefore reflects the parties' respective positions following the completion of the meet-and-confer process.
This Proposed Claim Constructions Chart is being filed simultaneously with, and is cross-referenced in, the Joint Claim Construction and Prehearing Statement filed under Patent Local Rule 4-3. OWS respectfully reserves the right to supplement or amend its proposed constructions to the extent permitted by the Court's scheduling order, the Patent Local Rules, and any further rulings of the Court.
SECTION I: U.S. Patent No. 10,234,567 ("the '567 Patent")
Title: "Integrated Waveguide Coupler with Tapered Mode Converter for Silicon Photonics Platforms"
Filing Date: March 14, 2017
Named Inventors: Dr. Kevin Fong, Dr. Priya Ramanathan, Hideo Tanaka
The '567 Patent is directed to an integrated optical coupler architecture for silicon photonics platforms. The patent generally describes a tapered silicon waveguide structure that provides efficient optical mode coupling to a silicon nitride waveguide layer, enabling low-loss light transfer between waveguide layers of different refractive indices. Three terms from the '567 Patent are in dispute.
Term 1: "adiabatically coupled"
Claim(s): 1, 4, 7, 12, 15
Full Claim Context (Claim 1):
"An integrated optical coupler comprising a tapered silicon waveguide having a tip width of less than 200 nanometers adiabatically coupled to a silicon nitride waveguide layer…"
OWS's Proposed Construction:
"coupled such that optical mode transitions occur without significant power loss"
Lumos's Proposed Construction:
"coupled through a gradual, continuous taper that prevents excitation of higher-order modes throughout the entire transition region"
OWS's Principal Supporting Evidence:
1. '567 Patent specification, col. 4, ll. 22–38. The specification describes "adiabatic coupling" in terms of the efficiency of power transfer between waveguide modes, stating that the coupler is designed to "transfer optical power between the silicon and silicon nitride waveguide layers with minimal loss." The specification's discussion of adiabatic coupling is framed in functional terms — focusing on power transfer efficiency — rather than in terms of any specific structural geometry of the taper.
2. '567 Patent specification, col. 6, ll. 5–19. In discussing various embodiments, the specification references "low-loss" coupling and describes multiple taper profiles (linear, exponential, and parabolic) that can achieve adiabatic coupling. The specification does not mandate or require any single taper geometry as a prerequisite to achieving "adiabatic" coupling, but instead describes adiabatic coupling as a performance characteristic achievable through range structural approaches.
3. Declaration of Dr. Harold Whitfield (Whitfield Technical Consulting Group, Inc.). Dr. Whitfield will offer the opinion that a person of ordinary skill in the art ("POSITA") working in the field of integrated photonics as of the filing date of the '567 Patent would understand the term "adiabatically coupled" to refer to a coupling configuration in which optical mode transitions occur without significant power loss — that is, a coupling in which optical energy is transferred from one waveguide mode to another while preserving the modal state and avoiding radiation or scattering losses. Dr. Whitfield will further testify that a POSITA would not understand the term to be limited to any single taper geometry (such as a continuous linear taper), as the term "adiabatic" in the context of optical waveguide coupling is well understood to be a functional descriptor of the coupling efficiency rather than a structural limitation on the taper shape.
4. Extrinsic evidence — technical dictionaries and photonics textbooks. Standard reference works in the field of photonics define the term "adiabatic" in the context of waveguide transitions as referring to gradual transitions that preserve the quantum or modal state of the light, without requiring continuity of any specific structural feature. See, e.g., B. E. A. Saleh & M. C. Teich, Fundamentals of Photonics (3d ed. 2019), at 321–22; A. Yariv & P. Yeh, Photonics: Optical Electronics in Modern Communications (6th ed. 2007), at 156–58. These sources confirm that the concept of "adiabatic" coupling is understood in terms of the mode transition behavior, not the precise geometry of the coupling structure.
Lumos's Principal Supporting Evidence:
1. '567 Patent prosecution history. During prosecution of the '567 Patent, the applicant amended Claim 1 to add the "adiabatically coupled" limitation in order to overcome a prior art rejection based on Tanaka, U.S. Patent No. 9,456,012 (issued September 6, 2016). Lumos contends that prosecution history estoppel limits the scope of "adiabatically coupled" because the applicant narrowed the claim to distinguish segmented and discrete coupling designs disclosed in Tanaka. In Tanaka, the coupler employed a segmented taper comprising a series of discrete sections rather than a continuous taper, and the applicant distinguished the claimed invention by emphasizing the adiabatic nature of the coupling — which Lumos contends necessarily requires a continuous, gradual taper.
2. '567 Patent specification, col. 5, ll. 10–28. In the preferred embodiment, the specification describes the taper as "gradual" and "continuous," stating that "the silicon waveguide is tapered gradually and continuously from its full width to the tip width, thereby ensuring adiabatic mode conversion." Lumos relies on this passage to argue that the patentee defined "adiabatically coupled" in terms of a gradual and continuous taper geometry.
3. Applicant's remarks in the prosecution history. In the applicant's response to the office action, the applicant stated that the claimed invention was distinguished from the Tanaka prior art because "the present invention employs an adiabatic coupling achieved through a continuous taper, unlike the segmented approach of Tanaka." Lumos contends that these remarks confirm that "adiabatically coupled" requires a continuous taper and cannot encompass segmented or discrete coupling designs.
4. Chen & Liu, "Segmented Taper Coupler Design for Low-Loss Fiber-to-Chip Coupling," Journal of Photonic Integration, Vol. 14, No. 3, pp. 217–229 (2016). Lumos cites this extrinsic evidence to demonstrate that segmented taper designs were known in the art and were treated as distinct from adiabatic taper designs. The article distinguishes "segmented" coupler architectures from "adiabatic" coupler architectures, which Lumos argues confirms the understanding that "adiabatically coupled" in the patent claims excludes segmented designs.
5. Declaration/testimony of Dr. Raymond Ng (Brannick Howell & Stein LLP, Of Counsel / Technical Consultant). Dr. Ng will offer the opinion that a POSITA would understand "adiabatically coupled" in the context of integrated waveguide couplers to require a gradual, continuous taper that prevents excitation of higher-order modes throughout the entire transition region. Dr. Ng will testify that the term carries a specific structural connotation in the field of silicon photonics, requiring continuity of the taper profile, and that a POSITA would distinguish "adiabatic" coupling from segmented or discrete coupling approaches.
Term 2: "tapered silicon waveguide having a tip width of less than 200 nanometers"
Claim(s): 1, 12
Full Claim Context (Claim 1):
"An integrated optical coupler comprising a tapered silicon waveguide having a tip width of less than 200 nanometers adiabatically coupled to a silicon nitride waveguide layer…"
OWS's Proposed Construction:
Plain and ordinary meaning; no construction necessary. Alternatively: "a silicon waveguide that narrows to a tip with a width below 200 nm"
Lumos's Proposed Construction:
"a single, unitary silicon waveguide structure that continuously narrows to a tip having a width measured at the narrowest point of less than 200 nm as fabricated"
OWS's Principal Supporting Evidence:
1. '567 Patent specification, col. 3, ll. 40–55. The specification describes the tip width as a design parameter for efficient mode coupling, stating that the tip width is selected to ensure that the optical mode is no longer confined in the silicon waveguide and is instead transferred to the underlying silicon nitride layer. The specification discusses the tip width as a functional parameter that may be optimized for particular coupling applications, without imposing a requirement that the waveguide be a "single, unitary" structure or that the tip width be measured under specific conditions (e.g., "as fabricated").
2. The claim language itself is clear and unambiguous and requires no construction beyond its plain and ordinary meaning. The claim recites "a tapered silicon waveguide having a tip width of less than 200 nanometers," which a POSITA would readily understand to mean a silicon waveguide that narrows (tapers) to a tip that is less than 200 nm wide. Lumos's proposed construction impermissibly imports limitations from the specification — specifically, the requirements that the waveguide be "single, unitary," that it "continuously" narrow, and that the tip width be measured "as fabricated" — that are not present in the claim language.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that the term "tapered silicon waveguide having a tip width of less than 200 nanometers" is well understood by a POSITA and does not require construction. Dr. Whitfield will further testify that a POSITA would not read the term to require a "single, unitary" waveguide structure, as the claims do not impose such a limitation, and that the phrase "as fabricated" — which appears nowhere in the claim language — impermissibly introduces a measurement-condition limitation that is unsupported by the intrinsic evidence.
Lumos's Principal Supporting Evidence:
1. '567 Patent specification, col. 5, ll. 30–45. The specification describes the preferred embodiment as including "a single waveguide structure that tapers from its full width at the input to a narrow tip at the coupling region." Lumos relies on this description to argue that the patentee contemplated a unitary, continuously tapering waveguide structure, and that the claim language should be construed accordingly.
2. Prosecution history. During an examiner interview, the applicant described the tapered waveguide as a "single structure" that narrows from the input width to the tip. Lumos contends that these statements confirm that the applicant understood the claim to require a single, unitary waveguide rather than a segmented or composite structure.
3. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that a POSITA would understand the term "tapered silicon waveguide" to imply a single, continuously narrowing structure, and that the phrase "as fabricated" appropriately clarifies that the 200 nm tip width limitation is a structural feature of the fabricated device rather than a theoretical or simulated dimension.
Term 3: "silicon nitride waveguide layer"
Claim(s): 1, 7, 15
Full Claim Context (Claim 1):
"…adiabatically coupled to a silicon nitride waveguide layer…"
OWS's Proposed Construction:
"a waveguide layer comprising silicon nitride (SiN or Si₃N₄)"
Lumos's Proposed Construction:
"a waveguide layer consisting essentially of stoichiometric silicon nitride (Si₃N₄) deposited as a single continuous film"
OWS's Principal Supporting Evidence:
1. '567 Patent specification, col. 4, ll. 1–15. The specification uses the term "silicon nitride" in a general sense without restricting the stoichiometry of the silicon nitride material. The specification describes the waveguide layer as "silicon nitride" and discusses its refractive index properties in the context of waveguide coupling, without specifying that the silicon nitride must be stoichiometric Si₃N₄ as opposed to silicon-rich or nitrogen-rich variants.
2. '567 Patent specification, col. 7, ll. 20–30. In describing various embodiments, the specification references both "SiN" and "Si₃N₄" compositions and indicates that the waveguide layer may be deposited by low-pressure chemical vapor deposition ("LPCVD") or plasma-enhanced chemical vapor deposition ("PECVD"), each of which can produce silicon nitride films of varying stoichiometry. The specification's use of both terms — "SiN" (a general descriptor for silicon nitride films of varying stoichiometry, commonly denoted SiNx) and "Si₃N₄" (the stoichiometric composition) — confirms that the patent does not limit the claim to stoichiometric silicon nitride.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand the term "silicon nitride waveguide layer" to encompass waveguide layers made of silicon nitride in its various stoichiometric and non-stoichiometric compositions, including SiNx films with varying nitrogen content. Dr. Whitfield will further testify that in the silicon photonics field, "silicon nitride" is commonly used as a general material descriptor that encompasses a range of compositions, and that Lumos's proposed limitation to "stoichiometric silicon nitride (Si₃N₄) deposited as a single continuous film" improperly narrows the claim by importing limitations from a single preferred embodiment.
Lumos's Principal Supporting Evidence:
1. '567 Patent specification, preferred embodiment. Lumos relies on the preferred embodiment descriptions in the '567 Patent, which reference Si₃N₄ as the material for the waveguide layer. Lumos contends that the specification's focus on Si₃N₄ in the detailed description indicates that the patentee intended "silicon nitride" to refer to the stoichiometric composition.
2. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that the term "silicon nitride waveguide" as used in industry standard practice refers to waveguides made of stoichiometric Si₃N₄, and that a POSITA would understand the claim language to require a stoichiometric composition deposited as a single continuous film. Dr. Ng will further testify that non-stoichiometric silicon nitride films (SiNx) have materially different optical properties, including higher optical absorption losses, and that a POSITA would therefore understand the patent's reference to "silicon nitride" to mean the stoichiometric form that is commonly used in photonic waveguide applications.
SECTION II: U.S. Patent No. 10,891,234 ("the '234 Patent")
Title: "Germanium-on-Silicon Photodetector with Graded Buffer Layer for Enhanced Responsivity"
Filing Date: September 8, 2017
Named Inventors: Dr. Kevin Fong, Dr. Amara Osei
The '234 Patent is directed to a germanium-on-silicon photodetector architecture that employs a graded buffer layer between the silicon substrate and the germanium absorber to manage lattice mismatch and thereby enhance responsivity at telecommunications wavelengths. Three terms from the '234 Patent are in dispute.
Term 4: "graded buffer layer having a continuously varying germanium concentration"
Claim(s): 1, 3, 5, 8, 11
Full Claim Context (Claim 1):
Claim 1 recites a germanium-on-silicon photodetector comprising, inter alia, "a graded buffer layer having a continuously varying germanium concentration" disposed between the silicon substrate and the germanium absorber layer, wherein the graded buffer layer serves to accommodate lattice mismatch between the silicon substrate and the germanium absorber.
OWS's Proposed Construction:
"a buffer layer in which the germanium concentration changes across the layer thickness"
Lumos's Proposed Construction:
"a buffer layer in which the germanium atomic fraction increases monotonically and without step changes from the silicon substrate interface to the absorber layer"
OWS's Principal Supporting Evidence:
1. '234 Patent specification, col. 5, ll. 8–25. The specification describes embodiments with both "continuously graded" and "step-graded" buffer layers, and indicates that either approach can be used to manage the lattice mismatch between the silicon substrate and the germanium absorber. In particular, the specification states that "the graded buffer layer may be formed with a continuously varying germanium concentration or with a step-graded concentration profile, wherein the germanium content is increased in discrete steps across the buffer layer thickness." This passage demonstrates that the patentee contemplated both continuous and step-graded approaches within the scope of the invention.
2. '234 Patent specification, col. 6, ll. 1–12. The specification further explains that "grading" of the buffer layer serves to manage lattice mismatch and reduce threading dislocation density, regardless of whether the grading is implemented as a smooth, continuous gradient or as a series of fine compositional steps that approximate a continuous change. The specification's focus on the functional purpose of the graded buffer — managing lattice mismatch — rather than the precise manner in which the grading is implemented, supports OWS's broader construction.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will offer the opinion that a POSITA in the field of semiconductor epitaxy and photodetector fabrication would understand the term "continuously varying" in the context of a graded buffer layer to mean that the germanium concentration changes across the thickness of the layer, encompassing both smooth gradients and fine step-grading that approximates a continuous change. Dr. Whitfield will testify that in practical semiconductor fabrication, a perfectly smooth continuous gradient is an idealization, and that actual epitaxially grown graded layers inherently involve discrete atomic layer deposition steps. Accordingly, Dr. Whitfield will testify that a POSITA would not interpret "continuously varying" to exclude fine step-graded profiles that functionally approximate a continuous gradient.
4. Prosecution history. The '234 Patent was allowed on the first office action following an examiner interview, without any narrowing amendments to the claims. The applicant did not disclaim step-graded buffer layer embodiments during prosecution, and no statements were made during prosecution that would support Lumos's narrow construction requiring a monotonically increasing gradient "without step changes."
Lumos's Principal Supporting Evidence:
1. Claim language itself. Lumos contends that the term "continuously varying" is distinct from "step-graded" or merely "varying," and that the word "continuously" has a specific mathematical and physical meaning: without discontinuities. Lumos argues that by using the modifier "continuously," the patentee deliberately chose language that distinguishes a smooth, continuous gradient from a step-graded profile, and that OWS's proposed construction impermissibly reads the word "continuously" out of the claim.
2. '234 Patent specification, col. 5, ll. 26–35. Lumos relies on a passage in the specification that distinguishes "continuous grading" from "step grading" as separate embodiments: "In a first embodiment, the buffer layer has a continuously graded germanium concentration. In a second embodiment, the buffer layer has a step-graded germanium concentration profile." Lumos contends that this passage demonstrates that the patentee recognized and drew a distinction between continuous grading and step grading, and that the claim language — which recites "continuously varying" — corresponds to the first embodiment and excludes step-graded profiles.
3. EP 3,234,567 A1 (Nordlicht Photonische GmbH, published August 2, 2017). Lumos cites this European patent application, which was identified as § 102(a)(2) prior art during prosecution of the '234 Patent, as disclosing step-graded germanium buffer layers for photodetector applications. Lumos argues that because the prior art disclosed step-graded buffer layers, the '234 Patent's use of the term "continuously varying" was intended to claim over step-graded approaches and to distinguish the claimed invention from the prior art.
4. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that a POSITA in the field of semiconductor epitaxy would understand "continuously varying" to mean a smooth, monotonic gradient without step changes, consistent with standard terminology in the field. Dr. Ng will further testify that "continuous" and "step-graded" are well-recognized and distinct categories of compositional grading in semiconductor buffer layers, and that a POSITA would not conflate the two.
Term 5: "germanium absorber layer"
Claim(s): 1, 5, 8
Full Claim Context (Claim 1):
Claim 1 recites a germanium-on-silicon photodetector comprising a silicon substrate, a graded buffer layer, and "a germanium absorber layer disposed on the graded buffer layer, wherein the germanium absorber layer absorbs incident optical radiation at wavelengths between 1300 nm and 1600 nm."
OWS's Proposed Construction:
Plain and ordinary meaning; "a layer of germanium or germanium-rich material that absorbs optical radiation"
Lumos's Proposed Construction:
"a layer consisting of substantially pure germanium (≥98% Ge atomic fraction) that serves as the primary photon absorption region"
OWS's Principal Supporting Evidence:
1. '234 Patent specification. The specification references the "germanium absorber" in general terms without specifying a purity threshold or minimum germanium atomic fraction. The specification does not contain any language requiring that the absorber layer consist of "substantially pure germanium" or any specific minimum germanium concentration such as ≥98% Ge. Lumos's proposed construction improperly imports a numerical limitation from nowhere in the intrinsic record.
2. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand "germanium absorber layer" to encompass layers of germanium or germanium-rich material (including, for example, SiGe alloys with high germanium content) that serve as the photon absorption region of a photodetector. Dr. Whitfield will further testify that there is no basis in the claim language or specification to read a ≥98% purity requirement into the claim, and that Lumos's proposed construction is inconsistent with the ordinary meaning of the term as understood by persons skilled in the art.
Lumos's Principal Supporting Evidence:
1. '234 Patent specification, embodiment descriptions. Lumos relies on the specification's descriptions of preferred embodiments, which describe the absorber layer as consisting of "pure germanium" deposited on the graded buffer layer. Lumos contends that the specification's consistent references to "germanium" (rather than "germanium-rich" or "SiGe") indicate that the patentee intended the absorber to be composed of substantially pure germanium.
2. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that in industry convention, a "germanium absorber" in the context of a germanium-on-silicon photodetector refers to an absorber layer composed of high-purity germanium, and that a POSITA would understand the term to imply a germanium atomic fraction of at least 98%. Dr. Ng will further testify that absorber layers with lower germanium content (e.g., SiGe alloys) are typically described as "SiGe absorber" layers rather than "germanium absorber" layers, and that the distinction is meaningful in the art.
Term 6: "enhanced responsivity"
Claim(s): Appears in the title of the '234 Patent and in the preamble of Claim 1.
Full Claim Context (Preamble of Claim 1):
"A germanium-on-silicon photodetector with enhanced responsivity, comprising…"
OWS's Proposed Construction:
Not a claim limitation; preamble language that does not limit claim scope. Alternatively, if the Court finds the preamble limiting: "improved photodetector responsivity compared to designs without the claimed graded buffer layer"
Lumos's Proposed Construction:
"a responsivity of at least 0.8 A/W at 1550 nm wavelength, achieved as a result of the claimed buffer layer structure"
OWS's Principal Supporting Evidence:
1. Preamble is not limiting. The preamble of Claim 1 states "A germanium-on-silicon photodetector with enhanced responsivity." The body of Claim 1 recites all of the structural and functional limitations of the claimed invention, including the silicon substrate, graded buffer layer, germanium absorber layer, and their spatial and structural relationships. The phrase "enhanced responsivity" in the preamble merely describes an intended result or benefit of the claimed structure; it does not recite an independent structural or functional limitation that gives "life, meaning, and vitality" to the claim. Under Catalina Marketing International, Inc. v. Quillon Corporation, 289 F.3d 801, 808 (Fed. Cir. 2002), preamble language is not limiting when the body of the claim defines a structurally complete invention and the preamble merely states a purpose or intended use. Here, the body of Claim 1 defines a complete photodetector structure, and "enhanced responsivity" merely states a purpose or result.
2. '234 Patent specification. The specification provides 0.8 A/W as one exemplary value of responsivity achieved by a particular embodiment of the invention. See '234 Patent, col. 8, ll. 5–15 (stating that "in one embodiment, the photodetector achieves an enhanced responsivity of at least 0.8 A/W at 1550 nm"). This passage describes one embodiment's performance; it does not define "enhanced responsivity" as requiring a minimum threshold of 0.8 A/W for all embodiments. Lumos's proposed construction improperly elevates a single embodiment's performance figure to a definitional requirement applicable to the entire claim.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would not read a specific numerical responsivity threshold from the preamble language "enhanced responsivity," and that the term as used in the preamble merely conveys the general concept that the claimed photodetector structure achieves improved responsivity relative to prior art designs that lack the claimed graded buffer layer.
Lumos's Principal Supporting Evidence:
1. '234 Patent specification, col. 8, ll. 5–15. Lumos relies on the specification's statement that the photodetector achieves "enhanced responsivity of at least 0.8 A/W" at 1550 nm wavelength as evidence that the patentee defined "enhanced responsivity" with reference to a specific numerical threshold. Lumos contends that this passage constitutes the patentee's own definition of the term.
2. Preamble gives life and meaning to the claim. Lumos argues that the preamble phrase "with enhanced responsivity" is essential to understanding the claimed invention and should be treated as a limiting claim element. Lumos contends that the preamble gives "life, meaning, and vitality" to the claim because it defines the purpose and scope of the invention — a photodetector that achieves enhanced responsivity as a direct result of the claimed structural features — and that without this preamble limitation, the claim would lack a meaningful inventive distinction over the prior art.
SECTION III: U.S. Patent No. 11,045,678 ("the '678 Patent")
Title: "Multi-Channel Optical Transceiver with Integrated Wavelength-Division Multiplexing on Silicon"
Filing Date: June 22, 2018
Named Inventors: Dr. Priya Ramanathan, Dr. Amara Osei, Liwei Zhang
The '678 Patent is directed to a multi-channel optical transceiver architecture that integrates wavelength-division multiplexing ("WDM") functionality on a single silicon die. The patent describes a silicon photonics-based transceiver in which the WDM multiplexer and demultiplexer elements are monolithically fabricated alongside the optical transmitter and receiver components, enabling a compact, high-density optical transceiver for data center and telecommunications applications. Two terms from the '678 Patent are in dispute.
Term 7: "integrated wavelength-division multiplexing element monolithically formed on a single silicon die"
Claim(s): 1, 2, 6, 9, 14
Full Claim Context (Claim 1):
Claim 1 recites a multi-channel optical transceiver comprising "an integrated wavelength-division multiplexing element monolithically formed on a single silicon die," the WDM element comprising at least one of an arrayed waveguide grating and a ring resonator-based multiplexer/demultiplexer.
OWS's Proposed Construction:
"a WDM component fabricated as part of the same semiconductor fabrication process on a single die"
Lumos's Proposed Construction:
"a WDM component formed during front-end-of-line processing within the same silicon substrate, excluding hybrid integration, flip-chip bonding, or any heterogeneous integration technique"
OWS's Principal Supporting Evidence:
1. '678 Patent specification, col. 4, ll. 10–30. The specification describes "monolithic integration" as fabrication of the WDM element on a common substrate during the semiconductor process flow, stating that "the WDM element is monolithically integrated on the same silicon die as the transmitter and receiver components, using standard silicon photonics fabrication processes." The specification describes monolithic integration in terms of fabrication on a common substrate during the same process flow — it does not limit monolithic integration to front-end-of-line ("FEOL") processing steps only.
2. '678 Patent specification, col. 7, ll. 1–18. The specification describes WDM elements formed using standard silicon photonics process steps including waveguide patterning, doping, and metallization. Notably, metallization is a back-end-of-line ("BEOL") processing step, and the specification's inclusion of metallization in its description of the monolithically formed WDM elements confirms that "monolithically formed" encompasses both FEOL and BEOL process steps. Lumos's proposed construction, which limits "monolithically formed" to FEOL processing, is inconsistent with the specification's own description of the fabrication process.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand "monolithically formed on a single silicon die" to mean that the WDM component is fabricated on the same die during the same semiconductor fabrication process flow, encompassing both FEOL processing (e.g., waveguide patterning and doping) and BEOL processing (e.g., metallization and interconnect formation). Dr. Whitfield will further testify that Lumos's proposed limitation to "FEOL processing" only has no basis in the claim language or specification, and that monolithic fabrication in the silicon photonics industry encompasses the full range of semiconductor fabrication steps performed on a single die, including both FEOL and BEOL processes.
4. Prosecution history. While the term "monolithically formed" was added by amendment during prosecution of the '678 Patent, the applicant's remarks in support of the amendment distinguished the claimed invention from heterogeneous bonding of separately fabricated optical components onto the silicon die. Specifically, the applicant stated: "The present invention is distinguished from heterogeneous integration approaches in which optical components are separately fabricated on a different substrate and then bonded or attached to the silicon die." The applicant's distinction was directed to the separate fabrication and subsequent attachment of components — not to the exclusion of BEOL processing steps or any particular phase of the monolithic fabrication process. Accordingly, prosecution history estoppel does not support Lumos's proposed limitation to FEOL-only processing.
Lumos's Principal Supporting Evidence:
1. '678 Patent prosecution history. Lumos relies on the prosecution history in which the applicant added the "monolithically formed" limitation by amendment to overcome a prior art rejection based on hybrid integration references. Lumos contends that the applicant's remarks during prosecution — stating that "the present invention is distinguished from heterogeneous integration approaches" — constitute a clear disclaimer of any integration approach that involves bonding, attaching, or otherwise combining separately fabricated components. Lumos argues that prosecution history estoppel limits the scope of "monolithically formed" to exclude all forms of heterogeneous integration, including flip-chip bonding, micro-transfer printing, and any other technique involving separately fabricated elements.
2. '678 Patent specification, col. 3, ll. 20–35 (Background Section). The specification's background section criticizes hybrid integration approaches as suffering from "increased assembly complexity, alignment challenges, and higher manufacturing cost" compared to monolithic integration. Lumos contends that this background discussion confirms that the patentee viewed "monolithic" and "hybrid" integration as mutually exclusive categories, and that the claim language "monolithically formed" was deliberately chosen to exclude hybrid approaches.
3. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that a POSITA would understand "monolithically formed" in the context of silicon photonics to require that the WDM element be fabricated entirely within the same substrate using standard semiconductor processing, excluding any heterogeneous bonding, flip-chip attachment, or transfer printing of separately fabricated optical components. Dr. Ng will testify that this understanding is consistent with the established distinction between "monolithic" and "heterogeneous" integration approaches in the silicon photonics literature.
4. Lumos's accused LumosBridge 800G platform. Lumos notes that its accused LumosBridge 800G transceiver platform uses micro-transfer-printed III-V gain elements that are bonded to the silicon photonic integrated circuit ("PIC"). Lumos contends that the scope of this claim term is directly relevant to the infringement dispute, as OWS's broader construction would encompass Lumos's heterogeneous integration approach, whereas Lumos's narrower construction would exclude it.
Term 8: "multi-channel optical transceiver"
Claim(s): 1, 6, 14
Full Claim Context (Claim 1):
"A multi-channel optical transceiver comprising an integrated wavelength-division multiplexing element monolithically formed on a single silicon die…"
OWS's Proposed Construction:
Plain and ordinary meaning; "an optical transceiver capable of transmitting and/or receiving on multiple wavelength channels"
Lumos's Proposed Construction:
"an optical transceiver that simultaneously transmits and receives on at least four independent wavelength channels using a single optical interface"
OWS's Principal Supporting Evidence:
1. Claim language. The claim language recites "multi-channel optical transceiver" without specifying a minimum number of channels or requiring that the transceiver simultaneously transmit and receive. The plain meaning of "multi-channel" is "having more than one channel," and the plain meaning of "optical transceiver" is a device capable of transmitting and/or receiving optical signals. The claim does not recite "at least four" channels, does not require simultaneous transmission and reception, and does not require a "single optical interface."
2. '678 Patent specification. The specification describes embodiments with four, eight, and sixteen wavelength channels, demonstrating that the invention is not limited to any particular number of channels. See '678 Patent, col. 6, ll. 10–25 (describing four-channel, eight-channel, and sixteen-channel embodiments). Lumos's proposed construction improperly limits the claim to a single preferred embodiment (the four-channel configuration) by reading a minimum channel count from the specification into the claim.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand "multi-channel optical transceiver" in accordance with its plain and ordinary meaning — an optical transceiver operating on multiple (i.e., more than one) wavelength channels — and that there is no basis to read in a requirement of "at least four" channels, simultaneous transmit/receive, or a "single optical interface."
Lumos's Principal Supporting Evidence:
1. '678 Patent specification, preferred embodiment. Lumos relies on the specification's preferred embodiment, which describes a four-channel transceiver implementation in detail. Lumos contends that the preferred embodiment informs the proper construction of "multi-channel" and that a POSITA would understand "multi-channel" in the context of WDM optical transceivers to mean at least four channels, consistent with standard WDM configurations used in data center and telecommunications applications.
2. '678 Patent Abstract. The Abstract of the '678 Patent references "four or more channels," which Lumos argues reflects the patentee's understanding that "multi-channel" requires at least four channels.
SECTION IV: U.S. Patent No. 11,312,890 ("the '890 Patent")
Title: "Driver Circuit Architecture for High-Speed Silicon Photonic Mach-Zehnder Modulators"
Filing Date: November 15, 2018
Named Inventors: Dr. Kevin Fong, Rajesh Iyer
The '890 Patent is directed to a driver circuit architecture for high-speed silicon photonic Mach-Zehnder modulators. The patent describes a pre-emphasis equalization stage that is electrically co-integrated with the Mach-Zehnder modulator on a common semiconductor substrate, enabling high-speed modulation with reduced parasitic impedance and improved signal integrity. Three terms from the '890 Patent are in dispute.
Term 9: "pre-emphasis equalization stage electrically co-integrated with the modulator on a common substrate"
Claim(s): 1, 5, 8, 13
Full Claim Context (Claim 1):
Claim 1 recites a driver circuit architecture for a silicon photonic Mach-Zehnder modulator, the driver circuit comprising "a pre-emphasis equalization stage electrically co-integrated with the modulator on a common substrate," wherein the pre-emphasis equalization stage compensates for frequency-dependent signal loss in the modulator.
OWS's Proposed Construction:
"an equalization circuit located on the same substrate as the modulator"
Lumos's Proposed Construction:
"an equalization circuit fabricated in the same semiconductor process as the modulator, sharing the same doping profiles and process layers, and electrically connected without bond wires, interposers, or package-level routing"
OWS's Principal Supporting Evidence:
1. '890 Patent specification, col. 5, ll. 1–20. The specification describes "co-integration" as placing the driver equalization circuit on the same substrate as the modulator to reduce parasitic impedance and improve high-frequency performance. The specification states that "by co-integrating the pre-emphasis equalization stage with the modulator on a common substrate, parasitic capacitance and inductance associated with off-chip interconnects are eliminated, enabling higher modulation speeds." The specification's description of co-integration focuses on the benefit of placing the equalization circuit on the same substrate as the modulator — not on the sharing of doping profiles or process layers.
2. '890 Patent specification, col. 6, ll. 25–40. The specification further describes the advantages of co-integration, including "reduced interconnect length between the equalization stage and the modulator phase shifters, lower power consumption, and improved impedance matching." Again, the specification describes co-integration in terms of physical proximity and shared substrate placement, without specifically mandating shared doping profiles or identical process layers. The specification's focus is on the functional benefits of co-integration — reduced parasitics and improved performance — not on specific manufacturing process constraints.
3. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand "electrically co-integrated with the modulator on a common substrate" to mean that the equalization circuit is fabricated on or placed on the same substrate as the modulator, such that the two are electrically connected via on-chip interconnects rather than off-chip connections. Dr. Whitfield will further testify that the claim does not require that the equalization circuit share the same doping profiles and process layers as the modulator, as these are manufacturing details not recited in the claim language. Dr. Whitfield will explain that in practice, co-integrated circuits on a common substrate may use different doping profiles for different functional blocks (e.g., the driver transistors and the modulator phase shifters may have different doping requirements), and that sharing of doping profiles is a manufacturing implementation detail, not a definitional requirement of "co-integration."
4. Prosecution history. During prosecution of the '890 Patent, the applicant added the "co-integrated…on a common substrate" limitation to distinguish prior art describing driver circuits that were "separately fabricated and bonded" to the modulator die. The applicant's remarks during prosecution focused on the distinction between separate fabrication (followed by bonding) and co-integration on a common substrate. The applicant did not describe "co-integration" as requiring shared doping profiles or process layers; rather, the distinction drawn was between a separately fabricated driver die that is subsequently attached to the modulator die (as in the prior art) and a co-integrated configuration in which the driver and modulator are on the same substrate. Accordingly, prosecution history estoppel limits the scope of the term to exclude separately fabricated and bonded configurations, but does not support Lumos's additional proposed limitations regarding shared doping profiles, process layers, or the exclusion of interposers.
Lumos's Principal Supporting Evidence:
1. '890 Patent prosecution history. Lumos relies on the prosecution history in which the "co-integrated" limitation was added during prosecution to overcome a prior art rejection based on Iyer & Patel, "Co-Design of Modulator Drivers and Silicon Photonic Mach-Zehnder Structures," IEEE Transactions on Circuits and Systems, Vol. 65, No. 8, pp. 2701–2713 (2018). The Iyer & Patel reference described separately fabricated CMOS driver circuits that were wire-bonded to silicon photonic Mach-Zehnder modulators. Lumos contends that the applicant's amendment adding "co-integrated" was specifically intended to exclude not only wire bonding but all forms of multi-die interconnection, including flip-chip bonding, interposers, and package-level routing.
2. Applicant's remarks during prosecution. During prosecution, the applicant stated: "The present invention is distinguished from approaches in which the driver circuit is separately fabricated and subsequently bonded or attached to the modulator die. In the claimed invention, the equalization stage is co-integrated with the modulator on a common substrate, eliminating the need for bond wires, flip-chip connections, or other off-chip interconnects." Lumos contends that these remarks expressly disclaimed flip-chip bonding and other multi-die connection approaches, and that the scope of "co-integrated" is accordingly limited to monolithic fabrication in a shared process flow.
3. '890 Patent specification, col. 4, ll. 30–45. Lumos relies on a passage in the specification describing co-integration as sharing "the same semiconductor processing sequence, doping profiles, and metallization layers," which Lumos contends constitutes the patentee's own definition of "co-integration." Lumos argues that this passage demonstrates that "co-integrated" in the '890 Patent requires not merely physical proximity on a common substrate, but fabrication in a shared semiconductor process flow with common doping profiles and process layers.
4. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that in the field of silicon photonics, "co-integrated" is a specific term of art meaning monolithic fabrication in a shared process flow, and that a POSITA would understand the term to require that the driver equalization circuit and the modulator be fabricated in the same semiconductor process, sharing the same doping profiles, process layers, and metallization. Dr. Ng will further testify that the term "co-integrated" is understood to exclude multi-die configurations in which the driver and modulator are separately fabricated and subsequently connected via bond wires, flip-chip bumps, interposers, or other package-level interconnects.
5. Lumos's accused product. Lumos notes that its accused product uses a separate CMOS driver die that is flip-chip bonded to the silicon photonic modulator die via copper pillar micro-bumps. Lumos contends that this product architecture falls outside the scope of the claim under Lumos's proposed construction, as the driver and modulator are separately fabricated and connected via flip-chip bonding rather than being co-integrated in a shared process flow on a common substrate.
Term 10: "pre-emphasis equalization stage"
Claim(s): 1, 5, 8
Full Claim Context (Claim 1):
"…a pre-emphasis equalization stage electrically co-integrated with the modulator on a common substrate…"
OWS's Proposed Construction:
"a circuit stage that applies pre-emphasis to compensate for frequency-dependent signal loss in the modulator"
Lumos's Proposed Construction:
"a feed-forward equalization circuit that applies a finite impulse response (FIR) filter with at least two taps to pre-compensate for bandwidth limitations of the Mach-Zehnder modulator"
OWS's Principal Supporting Evidence:
1. '890 Patent specification. The specification describes "pre-emphasis equalization" broadly, encompassing multiple equalization techniques and circuit topologies. The specification discusses pre-emphasis in terms of its functional purpose — compensating for frequency-dependent signal attenuation and bandwidth limitations in the modulator — rather than limiting pre-emphasis to any specific circuit implementation such as a FIR filter. The specification states: "The pre-emphasis equalization stage may be implemented using various circuit topologies, including but not limited to feed-forward equalization (FFE), continuous-time linear equalization (CTLE), or a combination thereof." See '890 Patent, col. 5, ll. 35–45. This passage confirms that the specification contemplates multiple equalization architectures, not just FIR-based feed-forward equalization.
2. Declaration of Dr. Harold Whitfield. Dr. Whitfield will testify that a POSITA would understand "pre-emphasis equalization stage" to encompass any circuit stage that applies pre-emphasis to compensate for frequency-dependent signal loss in the modulator, and would not limit the term to FIR filters or any specific number of filter taps. Dr. Whitfield will further testify that "pre-emphasis" is a general term in the field of high-speed modulator driver design that refers to the technique of boosting high-frequency signal components prior to modulation to compensate for bandwidth roll-off, and that this technique can be implemented using range circuit topologies including, but not limited to, FIR filters, CTLE circuits, and hybrid equalization architectures.
Lumos's Principal Supporting Evidence:
1. '890 Patent specification, preferred embodiment. Lumos relies on the specification's preferred embodiment, which describes a two-tap FIR pre-emphasis filter as the primary implementation of the pre-emphasis equalization stage. The specification provides detailed circuit-level descriptions of the two-tap FIR filter, including tap weights, delay elements, and summing nodes. Lumos contends that this detailed description indicates that the patentee equated "pre-emphasis equalization" with FIR-based feed-forward equalization.
2. Declaration/testimony of Dr. Raymond Ng. Dr. Ng will testify that "pre-emphasis equalization" in the context of high-speed Mach-Zehnder modulator drivers conventionally refers to FIR-based feed-forward equalization, and that a POSITA would understand the term as used in the '890 Patent to require a FIR filter with at least two taps. Dr. Ng will further testify that other equalization techniques such as CTLE are typically described using different terminology (e.g., "linear equalization" or "continuous-time equalization") and that the use of "pre-emphasis" in the patent specifically connotes a feed-forward, FIR-based approach.
Term 11: "common substrate"
Claim(s): 1, 13
Full Claim Context (Claim 1):