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EXHIBIT A

UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION

CERTIFIED COPY OF U.S. PATENT NO. 10,234,847

"Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss"

Filed as Exhibit A to Plaintiff's Original Complaint

Filed: April 22, 2024

Attorneys for Plaintiff Optiwave Semiconductor Corp.:

CALDERWOOD & HARKNESS LLP

Alan Ngo, Responsible Partner (CA Bar No. 246718) Marcus Delgado, Billing Partner (CA Bar No. 289543) 350 South Grand Avenue, 48th Floor Los Angeles, California 90071 Telephone: (213) 555-7200 Facsimile: (213) 555-7201

Email: ango@calderwoodharkness.com

Email: mdelgado@calderwoodharkness.com

Local Counsel:

WHITMORE & CALLAHAN LLP

James "Jim" Callahan (TX Bar No. 03891247) 110 North College Avenue, Suite 800 Tyler, Texas 75702 Telephone: (903) 555-1400 Facsimile: (903) 555-1401

Email: jcallahan@whitmorecallahan.com

UNITED STATES PATENT

US 10,234,847 B2

(54) MULTI-CHANNEL SILICON PHOTONIC WAVEGUIDE MULTIPLEXER WITH LOW INSERTION LOSS

(75) Inventors:

Jian-Wei Huang, Santa Clara, CA (US); Nikolai Petrov, Santa Clara, CA (US); Emily R. Vasquez, Sunnyvale, CA (US)

(73) Assignee: Optiwave Semiconductor Corp., Santa Clara, CA (US)

( ) Notice:* Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. § 154(b) by 0 days.

(21) Appl. No.: 15/265,418

(22) Filed: September 14, 2016

(65) Prior Publication Data

US 2017/0082808 A1 — March 23, 2017

Related U.S. Application Data

(63) Continuation-in-part of application No. 14/551,230, filed on November 22, 2014, now U.S. Pat. No. 9,678,562, issued June 13, 2017.

(60) Provisional application No. 62/086,471, filed on December 2, 2013.

(51) Int. Cl.

G02B 6/12 (2006.01) G02B 6/293 (2006.01) H04J 14/02 (2006.01)

(52) U.S. Cl.

CPC — G02B 6/12007 (2013.01); G02B 6/29344 (2013.01); H04J 14/0201 (2013.01); G02B 6/12004 (2013.01); G02B 6/29361 (2013.01)

(58) Field of Classification Search

CPC — G02B 6/12007; G02B 6/12004; G02B 6/29344; G02B 6/29361; H04J 14/0201; H04J 14/0208 USPC — 385/24, 37, 39, 46, 129, 130, 131; 398/79, 82, 83, 87 See application file for complete search history.

(56) References Cited

U.S. PATENT DOCUMENTS

FOREIGN PATENT DOCUMENTS

OTHER PUBLICATIONS

Takahashi, H. et al., "Low-Loss Silicon Photonic Waveguide Multiplexer with Sub-Decibel Insertion Loss," IEEE Photonics Technology Letters, Vol. 26, No. 6, pp. 601–604, March 15, 2014.

Bogaerts, W. et al., "Silicon microring resonators," Tidewater Group, Vol. 6, No. 1, pp. 47–73, 2012.

Pathak, S. et al., "Comparison of AWGs and Echelle Gratings for Wavelength Division Multiplexing on Silicon-on-Insulator," IEEE Photonics Journal, Vol. 6, No. 5, pp. 1–9, October 2014.

Doerr, C.R. et al., "Silicon photonics broadband modulation-based isolator," Optics Express, Vol. 22, No. 4, pp. 4493–4498, 2014.

Thomson, D. et al., "Roadmap on silicon photonics," Journal of Optics, Vol. 18, No. 7, 073003, 2016.

Cheben, P. et al., "Subwavelength integrated photonics," Nature, Vol. 560, pp. 565–572, 2018 (cited by applicant during prosecution).

(74) Attorney, Agent, or Firm — Cascade IP Advisors, LLC; Dr. Martin Chu, Lead Prosecution Attorney; 1550 Crystal Drive, Suite 600, Arlington, VA 22202

(57) ABSTRACT

A multi-channel silicon photonic waveguide multiplexer is disclosed that combines multiple optical signals of different wavelengths onto a single output waveguide with low insertion loss. The multiplexer is fabricated on a silicon-on-insulator (SOI) substrate using standard CMOS-compatible semiconductor fabrication processes. The device employs a novel waveguide geometry and coupling arrangement that achieves insertion loss below approximately 1.5 dB per channel across the C-band (1530–1565 nm) and L-band (1565–1625 nm) wavelength ranges. The multiplexer utilizes tapered waveguide transitions and mode-matching structures at the coupling region to minimize modal mismatch and reduce scattering losses. The multiplexer is suitable for integration into optical transceiver modules for data-center interconnect applications, supporting dense wavelength-division multiplexing (DWDM) with channel counts of 4, 8, or 16 channels. The device is scalable through a cascaded coupling-stage architecture and is compatible with high-volume semiconductor manufacturing processes.

9 Drawing Sheets 14 Claims

DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a multi-channel silicon photonic waveguide multiplexer in accordance with an embodiment of the present invention, showing a plurality of input waveguides (102a–102h), a coupling region (104), and a single output waveguide (106), illustrating the general architecture of the multiplexer device.

FIG. 2 is a cross-sectional view of the silicon-on-insulator (SOI) waveguide structure employed in the multiplexer of FIG. 1, taken along the line A-A′, showing the silicon core (202), the buried oxide (Box) layer (204), the silicon handle wafer (206), and the upper cladding layer (208), with dimensions of the waveguide core annotated in nanometers.

FIG. 3 is a top-view layout of an 8-channel waveguide multiplexer embodiment in accordance with the present invention, showing the arrangement of input ports (302a–302h), waveguide routing paths (304), the coupling region (306), and the output port (308).

FIG. 4 is a detailed view of the coupling region (104) of the waveguide multiplexer of FIG. 1, illustrating the tapered waveguide transitions (402) and mode-matching structures (404) that reduce insertion loss at the interface between the input waveguides and the coupling region.

FIG. 5 is a graph plotting measured insertion loss in decibels (dB) versus wavelength in nanometers (nm) across the C-band (1530–1565 nm) for each of the 8 channels (Ch. 1 through Ch. 8) of the waveguide multiplexer embodiment of FIG. 3, demonstrating that insertion loss remains below 1.5 dB per channel across the measured wavelength range.

FIG. 6 is a graph plotting channel crosstalk in decibels (dB) versus wavelength in nanometers (nm) for the 8-channel embodiment of FIG. 3, showing adjacent-channel crosstalk levels below −25 dB across the C-band wavelength range.

FIG. 7 is a schematic diagram of an optical transceiver module incorporating the waveguide multiplexer of the present invention, showing integration of the multiplexer (702) with laser sources (704), optical modulators (706), and photodetectors (708) on a silicon photonic integrated circuit (PIC) (710).

FIG. 8 is a top-view layout of an alternative embodiment of the present invention, showing a 16-channel waveguide multiplexer (800) with a cascaded arrangement of coupling stages (802a, 802b) for multiplexing 16 input channels onto a single output waveguide.

FIG. 9 is a block diagram of a system-level embodiment showing the waveguide multiplexer (902) of the present invention integrated into a data-center interconnect link, with a transmitter module (904) and a receiver module (906) connected via a single-mode fiber (908), illustrating the end-to-end optical communication architecture.

[Note: Figures are not reproduced in this text version. Reference is made to the original patent document as filed with the USPTO, which includes nine sheets of drawings corresponding to FIGS. 1–9 described above.]

SPECIFICATION

MULTI-CHANNEL SILICON PHOTONIC WAVEGUIDE MULTIPLEXER WITH LOW INSERTION LOSS

FIELD OF THE INVENTION

The present invention relates generally to silicon photonic devices, and more particularly to multi-channel waveguide multiplexers for combining multiple wavelength channels onto a single optical waveguide with low insertion loss. The invention is directed to devices suitable for use in optical transceiver modules and data-center interconnect applications employing dense wavelength-division multiplexing (DWDM) techniques. The invention further relates to silicon-on-insulator (SOI) based photonic integrated circuits (PICs) and methods for fabricating waveguide multiplexer structures using CMOS-compatible semiconductor manufacturing processes.

BACKGROUND OF THE INVENTION

The explosive growth of cloud computing, artificial intelligence workloads, and streaming media services has driven unprecedented demand for high-bandwidth optical interconnects within and between hyperscale data centers. Modern hyperscale data centers operated by major cloud service providers require interconnect solutions capable of supporting data rates of 400 Gbps, 800 Gbps, and beyond over distances ranging from intra-rack connections of a few meters to campus-scale links spanning tens of kilometers. Silicon photonics has emerged as a leading platform for implementing these high-bandwidth optical interconnect solutions due to the technology's compatibility with established CMOS semiconductor manufacturing infrastructure, which enables high-volume production at significantly lower cost per device than competing photonic platforms based on indium phosphide (InP) or other III-V compound semiconductor materials.

A critical component in high-bandwidth optical interconnect systems is the wavelength-division multiplexer, which combines multiple optical signals at different wavelengths onto a single optical fiber or waveguide. The multiplexer reduces the number of physical fibers required for a given aggregate bandwidth by allowing multiple data channels to share a single fiber, with each channel operating at a distinct wavelength within the optical transmission window. Dense wavelength-division multiplexing (DWDM) systems operating in the C-band (approximately 1530 to 1565 nm) and L-band (approximately 1565 to 1625 nm) can support 8, 16, 32, or more channels on a single fiber, with channel spacings as narrow as 100 GHz or less.

Several approaches to implementing waveguide multiplexers on silicon photonic platforms have been reported in the prior art. Arrayed waveguide gratings (AWGs) represent one widely studied approach. An AWG consists of a set of input waveguides coupled to a first slab coupler (also referred to as a free propagation region), an array of waveguides with carefully controlled path-length differences (the phased array), a second slab coupler, and a set of output waveguides. The operation of an AWG relies on the constructive and destructive interference of optical signals propagating through the phased array to achieve wavelength-selective routing of individual channels to designated output ports. While AWGs can achieve high channel counts, they are subject to significant insertion loss, particularly when fabricated on silicon-on-insulator platforms where the high index contrast between the silicon core and the silicon dioxide cladding amplifies the effects of waveguide sidewall roughness and dimensional variations. Typical insertion losses for silicon-based AWGs reported in the literature range from 2 dB to 5 dB or more per channel, which is unacceptable for many high-performance transceiver applications.

Echelle gratings, also known as planar concave gratings, represent an alternative approach to wavelength-division multiplexing on silicon platforms. Echelle gratings use a single reflecting surface with a periodic corrugation to diffract different wavelengths to different spatial locations, where they are collected by output waveguides. While echelle gratings can be compact and are capable of supporting a moderate number of channels, they are sensitive to fabrication variations in the grating facet profile and tend to exhibit higher insertion loss and poorer crosstalk performance than AWGs when implemented in high-index-contrast silicon waveguide platforms.

Mach-Zehnder interferometer (MZI) based multiplexers represent a third approach, in which cascaded stages of MZI filters are used to separate or combine wavelength channels. MZI-based multiplexers offer the advantage of relatively simple design and good spectral flatness within each channel passband, but the cascaded architecture results in a device that grows in size and complexity with increasing channel count, and the cumulative insertion loss of multiple MZI stages can be substantial.

Each of these existing approaches suffers from one or more significant limitations when implemented on silicon-on-insulator platforms for high-volume manufacturing. High insertion loss degrades the power budget of the optical link, reducing the maximum achievable transmission distance or requiring the use of higher-power laser sources that increase cost and power consumption. Manufacturing variability inherent in CMOS fabrication processes introduces channel-to-channel non-uniformity in insertion loss and center wavelength, reducing yield and necessitating costly post-fabrication trimming or calibration procedures. Limited channel count restricts the aggregate bandwidth that can be supported on a single fiber, requiring additional fibers and associated optical connectors that increase system cost and complexity.

There is therefore a need in the art for a CMOS-compatible waveguide multiplexer that achieves low insertion loss across a broad wavelength range while supporting high channel counts, and that is suitable for integration into high-volume silicon photonic transceiver modules for data-center interconnect and telecommunications applications.

SUMMARY OF THE INVENTION

The present invention provides a multi-channel silicon photonic waveguide multiplexer fabricated on a silicon-on-insulator (SOI) substrate that addresses the limitations of existing waveguide multiplexer designs. The waveguide multiplexer of the present invention combines multiple optical signals of different wavelengths onto a single output waveguide with insertion loss below approximately 1.5 dB per channel across a wavelength range spanning at least the C-band (1530–1565 nm).

In accordance with one aspect of the invention, the waveguide multiplexer comprises a plurality of input waveguides, each configured to receive an optical signal at a respective wavelength, and a coupling region configured to combine the optical signals from the plurality of input waveguides onto a single output waveguide. Tapered waveguide transitions are disposed between the input waveguides and the coupling region and are configured to provide adiabatic mode conversion that reduces insertion loss at the interface between the input waveguides and the coupling region. The tapered waveguide transitions achieve mode matching between the narrower input waveguides and the wider waveguide structures within the coupling region, thereby minimizing modal mismatch loss and reducing back-reflection.

In accordance with another aspect of the invention, mode-matching structures are provided within the coupling region that further reduce insertion loss by ensuring efficient power transfer between the input modes and the output mode of the output waveguide. The mode-matching structures may include tapered slab regions, multimode interference (MMI) couplers, or other structures configured to minimize scattering and radiation losses at waveguide junctions.

The waveguide multiplexer of the present invention is scalable to support channel counts of 4, 8, or 16 channels, with optimized channel spacing of approximately 200 GHz or 400 GHz for compatibility with standard DWDM wavelength grids. For channel counts exceeding 8, the multiplexer may employ a cascaded arrangement of coupling stages, wherein a first set of coupling stages combines groups of input channels and a second coupling stage combines the outputs of the first set of coupling stages onto the single output waveguide.

The waveguide multiplexer is fabricated using semiconductor fabrication processes that are fully compatible with standard CMOS foundry manufacturing, including photolithographic patterning, reactive ion etching, chemical vapor deposition, and chemical mechanical planarization. This compatibility enables high-volume manufacturing of the waveguide multiplexer at established CMOS foundries, achieving economies of scale and cost structures that are not attainable with photonic devices fabricated on non-silicon platforms.

The waveguide multiplexer of the present invention is particularly suitable for integration into optical transceiver modules for data-center interconnect applications, including 400G-ZR, 400G-DR4, 800G-DR8, and other standardized transceiver form factors. The waveguide multiplexer may be monolithically integrated with other silicon photonic components, including laser sources, optical modulators, photodetectors, and electronic driver and receiver circuits, on a single silicon photonic integrated circuit (PIC).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following detailed description sets forth specific embodiments of the present invention with reference to the accompanying drawings. The description is not intended to limit the scope of the invention, which is defined by the appended claims. Those skilled in the art will recognize that various modifications and alternative implementations are possible without departing from the spirit and scope of the invention as defined by the claims.

1. Waveguide Structure

Referring now to FIG. 2, the waveguide multiplexer of the present invention is fabricated on a silicon-on-insulator (SOI) platform. The SOI substrate comprises a silicon handle wafer 206, a buried oxide (Box) layer 204 disposed on the silicon handle wafer 206, and a silicon device layer disposed on the box layer 204. The silicon device layer is patterned to form the silicon core 202 of the optical waveguides. An upper cladding layer 208, which may comprise silicon dioxide (SiO₂) deposited by plasma-enhanced chemical vapor deposition (PECVD) or other suitable deposition technique, is disposed over the patterned silicon core 202.

In a preferred embodiment, the silicon core 202 has a thickness of approximately 220 nm and a width that varies depending on the specific waveguide function. For single-mode operation at C-band wavelengths, the waveguide width is approximately 450 nm to 500 nm. The box layer 204 has a thickness of approximately 2 µm to 3 µm, which provides sufficient optical isolation from the silicon handle wafer 206 to prevent leakage of the guided optical mode into the substrate. The upper cladding layer 208 has a thickness of approximately 1.5 µm to 3 µm.

The waveguide dimensions are selected to ensure single-mode operation for the transverse-electric (TE) polarization at wavelengths within the C-band and L-band. The high index contrast between the silicon core (refractive index approximately 3.48 at 1550 nm) and the silicon dioxide cladding (refractive index approximately 1.44 at 1550 nm) provides strong optical confinement, enabling tight waveguide bends with radii as small as 5 µm with acceptable radiation loss. However, the high index contrast also amplifies the effects of waveguide sidewall roughness on scattering loss. The present invention addresses this challenge through specific design features described in the sections below.

The waveguide structures are fabricated using standard CMOS-compatible semiconductor fabrication processes. The silicon device layer is patterned using deep-ultraviolet (DUV) photolithography with 193 nm or 248 nm illumination, followed by reactive ion etching (RIE) to define the waveguide core. The etch process is optimized to achieve smooth sidewall profiles with root-mean-square (RMS) roughness below approximately 2 nm, which minimizes scattering loss. The upper cladding layer is deposited by PECVD and planarized by chemical mechanical planarization (CMP) to provide a smooth surface for subsequent processing steps or for flip-chip bonding of laser die.

In alternative embodiments, the upper cladding layer 208 may comprise silicon nitride (Si₃N₄) or a combination of silicon dioxide and silicon nitride layers. Silicon nitride cladding offers a lower index contrast with the silicon core compared to silicon dioxide cladding, which can reduce scattering sensitivity to sidewall roughness in certain waveguide geometries. The selection of cladding material may be optimized based on the specific requirements of the multiplexer design and the available fabrication process at the target CMOS foundry.

2. Multiplexer Architecture

Referring now to FIG. 1 and FIG. 3, the waveguide multiplexer 100 of the present invention comprises a plurality of input waveguides 102a–102h, a coupling region 104, and a single output waveguide 106. In the 8-channel embodiment illustrated in FIG. 3, eight input waveguides 302a–302h are routed from input ports 302a–302h at the periphery of the photonic integrated circuit to the coupling region 306, where the optical signals carried by the eight input waveguides are combined onto the single output waveguide leading to output port 308.

Each input waveguide 102a–102h is configured to receive an optical signal at a respective wavelength λ₁ through λ₈, where the wavelengths are assigned according to a standard DWDM wavelength grid. In a preferred embodiment, the channel spacing is approximately 200 GHz (approximately 1.6 nm at 1550 nm center wavelength), providing compatibility with ITU-T G.694.1 DWDM wavelength grids. In an alternative embodiment, the channel spacing is approximately 400 GHz (approximately 3.2 nm), which may be preferred in applications where reduced channel count or wider passband is acceptable.

The coupling region 104 is the portion of the multiplexer where the optical signals from the plurality of input waveguides are combined onto the single output waveguide 106. The present invention is not limited to a specific coupling architecture within the coupling region. In one embodiment, the coupling region employs an arrayed waveguide grating (AWG) architecture comprising a first slab coupler, a phased array of waveguides with controlled path-length differences, and a second slab coupler. In another embodiment, the coupling region employs a cascaded Mach-Zehnder interferometer (MZI) architecture. In yet another embodiment, the coupling region employs a star coupler or multimode interference (MMI) coupler architecture. The selection of coupling architecture may be based on the specific requirements of the application, including channel count, channel spacing, passband shape, and die area constraints.

Regardless of the specific coupling architecture employed within the coupling region, the waveguide multiplexer of the present invention includes tapered waveguide transitions and mode-matching structures at the interfaces between the input waveguides and the coupling region, as described in detail below with reference to FIG. 4. These interface structures are a key innovation of the present invention and are responsible for achieving the low insertion loss performance that distinguishes the present invention from prior-art waveguide multiplexers.

The waveguide routing paths 304 between the input ports and the coupling region are designed with optimized bend radii to minimize radiation loss at waveguide bends. In a preferred embodiment, the minimum bend radius is approximately 10 µm, which provides a radiation loss below 0.01 dB per 90-degree bend for the TE fundamental mode at C-band wavelengths. The waveguide routing paths are arranged to minimize crossings between waveguides, and where crossings are unavoidable, the crossings are implemented using waveguide intersection designs that minimize crosstalk and insertion loss.

3. Low Insertion Loss Design

Referring now to FIG. 4, the waveguide multiplexer of the present invention achieves low insertion loss through several specific design features that collectively reduce the dominant loss mechanisms in silicon photonic waveguide multiplexers.

Adiabatic Tapers. Tapered waveguide transitions 402 are disposed at the interfaces between the input waveguides 102a–102h and the coupling region 104. Each tapered waveguide transition 402 comprises an adiabatic taper in which the waveguide width is gradually varied from the width of the input waveguide (e.g., approximately 450 nm) to the width required at the entrance to the coupling region (e.g., approximately 1.5 µm to 3 µm, depending on the coupling architecture). The taper profile is designed to be adiabatic, meaning that the rate of change of the waveguide width is sufficiently gradual that substantially all optical power remains in the fundamental guided mode throughout the transition, with negligible excitation of higher-order modes or radiation modes. In a preferred embodiment, the taper length is at least 50 µm, and more preferably at least 100 µm, to ensure adiabatic operation across the full C-band wavelength range. The taper profile may be linear, parabolic, exponential, or a combination thereof, optimized to minimize insertion loss for a given taper length.

Mode-Matching Structures. Mode-matching structures 404 are provided within the coupling region 104 at the junctions between the tapered waveguide transitions 402 and the internal structures of the coupling region (e.g., the slab coupler in an AWG embodiment, or the input ports of an MMI coupler). The mode-matching structures 404 are configured to minimize modal mismatch between the guided mode at the output of the tapered waveguide transition and the mode of the coupling region structure. In one embodiment, the mode-matching structures comprise short sections of waveguide with intermediate dimensions that provide a stepped transition between the taper output and the coupling region. In another embodiment, the mode-matching structures comprise tapered slab regions that gradually transition from a channel waveguide geometry to a slab waveguide geometry. The mode-matching structures reduce the fraction of optical power that is scattered into radiation modes at the junction, thereby reducing insertion loss.

Optimized Bend Radii. All waveguide bends in the multiplexer are designed with radii optimized to balance radiation loss and device footprint. In the preferred embodiment, the minimum bend radius is 10 µm for standard single-mode waveguides and 20 µm for wider multimode waveguides in the coupling region. These bend radii provide radiation losses below 0.01 dB per bend at C-band wavelengths.

Reduced Sidewall Scattering Loss. The waveguide structures in the multiplexer are fabricated using an optimized etch process that achieves sidewall RMS roughness below 2 nm. Additionally, the waveguide width in the coupling region and in the phased-array waveguides (in the AWG embodiment) is wider than the minimum single-mode width, which reduces the overlap of the guided mode with the rough sidewalls and thereby reduces scattering loss per unit length. The combination of smooth sidewalls and reduced mode-sidewall overlap results in propagation loss below 1 dB/cm in the multiplexer waveguides.

Referring now to FIG. 5, the measured insertion loss of the 8-channel waveguide multiplexer embodiment of FIG. 3 is plotted as a function of wavelength across the C-band for each of the 8 channels. The measured data demonstrates that insertion loss remains below 1.5 dB per channel for all 8 channels across the wavelength range from 1530 nm to 1565 nm. The minimum insertion loss is approximately 0.8 dB, observed for the center channels (Ch. 4 and Ch. 5), while the edge channels (Ch. 1 and Ch. 8) exhibit slightly higher insertion loss of approximately 1.3 dB due to increased slab-diffraction loss at the extremes of the wavelength range. These results represent a significant improvement over prior-art silicon photonic AWGs, which typically exhibit insertion losses of 2 dB to 5 dB per channel.

Referring now to FIG. 6, the measured crosstalk performance of the 8-channel embodiment is plotted as a function of wavelength. The adjacent-channel crosstalk is below −25 dB for all channels across the C-band, and the non-adjacent-channel crosstalk is below −35 dB. These crosstalk levels meet the requirements of standard DWDM transceiver specifications, including OIF 400ZR and IEEE 802.3 standards.

4. Integration into Transceiver Modules

Referring now to FIG. 7, the waveguide multiplexer of the present invention is designed for monolithic or hybrid integration into silicon photonic transceiver modules for data-center interconnect applications. In the embodiment illustrated in FIG. 7, the waveguide multiplexer 702 is integrated onto a silicon photonic integrated circuit (PIC) 710 along with a plurality of optical modulators 706, at least one laser source 704, and a plurality of photodetectors 708.

The laser source 704 may comprise a distributed feedback (DFB) laser or an external cavity laser that is bonded to the PIC using flip-chip bonding, wafer-level bonding, or other hybrid integration techniques. In an alternative embodiment, the laser source may be integrated monolithically on the SOI platform using heterogeneous integration of III-V gain materials. The laser source provides a multi-wavelength optical carrier that is distributed to the plurality of optical modulators via a network of waveguide splitters or, in certain embodiments, via a comb laser source that generates multiple wavelength tones simultaneously.

The optical modulators 706 may comprise Mach-Zehnder modulators (MZMs), ring modulators, or electro-absorption modulators (EAMs), each configured to encode data onto the optical carrier at the respective wavelength. The modulated optical signals from the modulators are routed via the input waveguides to the waveguide multiplexer 702, which combines the modulated signals onto the single output waveguide for coupling to an output fiber.

On the receiver side, a corresponding waveguide demultiplexer (which may have the same architecture as the multiplexer, operated in reverse) separates the received wavelength channels, and the individual channel signals are directed to the photodetectors 708 for optical-to-electrical conversion. The photodetectors may comprise germanium (Ge) photodiodes monolithically integrated on the SOI platform.

The silicon photonic integrated circuit 710 may be packaged as a pluggable transceiver module in standard form factors, including QSFP-DD, OSFP, and CFP2-DCO, for deployment in data-center switches and routers. The transceiver module may comply with industry-standard specifications including OIF 400ZR, Open ROADM, IEEE 802.3bs (400GBASE-DR4), and IEEE 802.3ck (800GBASE-DR8), among others.

The waveguide multiplexer architecture of the present invention is particularly well-suited for integration into next-generation transceiver module configurations operating at aggregate data rates of 400 Gbps, 800 Gbps, and 1.6 Tbps. In a 400G-ZR transceiver module, the multiplexer combines four modulated wavelength channels, each carrying 100 Gbps, onto a single output fiber. In an 800G-DR transceiver module, the multiplexer combines eight modulated wavelength channels, each carrying 100 Gbps, onto a single output fiber. In future 1.6 Tbps transceiver modules, the multiplexer combines sixteen modulated wavelength channels using the cascaded coupling stage architecture described below.

5. Alternative Embodiments

4-Channel Configuration. In a first alternative embodiment, the waveguide multiplexer comprises four input waveguides and is configured to combine four wavelength channels onto a single output waveguide. The 4-channel configuration is suitable for 400G-DR4 transceiver modules and other lower-bandwidth applications where a reduced channel count is sufficient. The 4-channel configuration offers reduced die area and simplified waveguide routing compared to the 8-channel embodiment.

16-Channel Cascaded Configuration. Referring now to FIG. 8, in a second alternative embodiment, the waveguide multiplexer 800 comprises sixteen input waveguides and employs a cascaded arrangement of coupling stages 802a, 802b for multiplexing sixteen input channels onto a single output waveguide. In this embodiment, a first set of coupling stages 802a comprises two 8-channel multiplexers, each combining eight input channels onto a respective intermediate waveguide. A second coupling stage 802b combines the two intermediate waveguides onto the single output waveguide. The cascaded architecture enables scaling to 16 or more channels while maintaining the low insertion loss performance of each individual coupling stage. The total insertion loss of the 16-channel cascaded multiplexer is the sum of the insertion loss of the 8-channel stage (less than 1.5 dB) and the insertion loss of the 2-channel combining stage (less than 0.5 dB), resulting in a total insertion loss below approximately 2.0 dB per channel.

Silicon Nitride Cladding Variations. In a third alternative embodiment, the upper cladding layer comprises silicon nitride (Si₃N₄) rather than silicon dioxide. The lower index contrast between silicon and silicon nitride, compared to silicon and silicon dioxide, reduces the sensitivity of the multiplexer performance to waveguide sidewall roughness and dimensional variations. This embodiment may be preferred for applications requiring the tightest possible insertion loss specifications.

System-Level Embodiment. Referring now to FIG. 9, in a system-level embodiment, the waveguide multiplexer 902 of the present invention is integrated into a data-center interconnect link comprising a transmitter module 904 and a receiver module 906 connected via a single-mode fiber 908. The transmitter module 904 comprises the waveguide multiplexer 902 together with laser sources, modulators, and electronic driver circuits. The receiver module 906 comprises a corresponding waveguide demultiplexer together with photodetectors and transimpedance amplifier (TIA) circuits. The single-mode fiber 908 may have a length ranging from 500 meters to 120 kilometers, depending on the transceiver specification. The low insertion loss of the waveguide multiplexer 902 contributes directly to the link power budget, enabling longer transmission distances or reduced laser power consumption compared to systems employing prior-art waveguide multiplexers with higher insertion loss.

6. Relationship to Thermal Management

The performance of silicon photonic waveguide multiplexers is sensitive to temperature variations due to the thermo-optic coefficient of silicon (approximately 1.86 × 10⁻⁴ /°C at 1550 nm). Temperature changes shift the center wavelength of each channel in the multiplexer, which can degrade insertion loss and crosstalk performance if the channel wavelengths shift outside the passband. The waveguide multiplexer of the present invention is designed to operate over a temperature range of 0°C to 70°C with the aid of appropriate thermal management solutions.

Thermal management solutions for the waveguide multiplexer are described in detail in related U.S. Patent No. 9,678,562 (the '562 Patent), entitled "Method for Thermal Management of Photonic Integrated Circuits Using Embedded Micro-Channel Heat Sinks," filed November 22, 2014, issued June 13, 2017, which is a parent application of the present application and is hereby incorporated by reference in its entirety. The '562 Patent discloses embedded micro-channel heat sinks that provide localized temperature control of the photonic integrated circuit, enabling the waveguide multiplexer to maintain stable channel wavelengths over the required operating temperature range. The thermal management techniques disclosed in the '562 Patent are complementary to the waveguide multiplexer design disclosed in the present application, and the two inventions may be implemented together on a single silicon photonic integrated circuit to provide a complete multiplexer solution with integrated thermal management.

The present application is a continuation-in-part of the application that issued as the '562 Patent, and claims priority through this continuation chain to the provisional application filed December 2, 2013.

INDUSTRIAL APPLICABILITY

The multi-channel silicon photonic waveguide multiplexer of the present invention is applicable to a wide range of optical communication applications, including without limitation: hyperscale data-center interconnects operating at aggregate data rates of 400 Gbps, 800 Gbps, 1.6 Tbps, and beyond; metropolitan-area telecom networks employing DWDM technology; long-haul fiber-optic communication systems; campus-scale optical interconnects; and high-performance computing cluster interconnects. The CMOS-compatible fabrication process enables high-volume manufacturing at established semiconductor foundries, providing a cost-effective solution for mass-market deployment of silicon photonic transceiver modules.

CLAIMS

What is claimed is:

1. A multi-channel silicon photonic waveguide multiplexer, comprising:

a silicon-on-insulator substrate comprising a silicon device layer disposed on a buried oxide layer;

a plurality of input waveguides formed in the silicon device layer, each input waveguide configured to receive an optical signal at a respective wavelength;

a coupling region configured to combine the plurality of optical signals of different wavelengths from the plurality of input waveguides onto a single output waveguide formed in the silicon device layer;

a plurality of tapered waveguide transitions disposed between the plurality of input waveguides and the coupling region, each tapered waveguide transition configured to gradually vary a waveguide width from a width of a respective input waveguide to a width at an entrance to the coupling region, wherein the tapered waveguide transitions reduce insertion loss at the interface between the input waveguides and the coupling region;

wherein the waveguide multiplexer achieves an insertion loss of less than approximately 1.5 dB per channel across a wavelength range of at least 35 nm; and

wherein the waveguide multiplexer is fabricated using semiconductor fabrication processes compatible with complementary metal-oxide-semiconductor (CMOS) manufacturing.

2. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the plurality of input waveguides comprises at least 8 input waveguides, each configured to receive an optical signal at a respective one of at least 8 different wavelengths.

3. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a mode-matching structure disposed in the coupling region and configured to minimize modal mismatch between the plurality of input waveguides and the single output waveguide, wherein the mode-matching structure comprises at least one of a tapered slab region, a multimode interference coupler section, or a stepped waveguide transition configured to provide a gradual transition between a channel waveguide geometry and a slab waveguide geometry within the coupling region.

4. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein a channel spacing between adjacent ones of the respective wavelengths is approximately 200 GHz or approximately 400 GHz, corresponding to a standard dense wavelength-division multiplexing (DWDM) wavelength grid.

5. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein each of the plurality of tapered waveguide transitions comprises an adiabatic taper having a taper length of at least 50 µm, the adiabatic taper configured such that substantially all optical power remains in a fundamental guided mode throughout the tapered waveguide transition.

6. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the silicon device layer of the silicon-on-insulator substrate has a thickness of between 200 nm and 300 nm.

7. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the waveguide multiplexer achieves an insertion loss of less than approximately 1.0 dB per channel across the wavelength range of at least 35 nm.

8. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a wavelength-tuning element operably coupled to at least one of the plurality of input waveguides or to the coupling region, the wavelength-tuning element configured to adjust a center wavelength of at least one channel of the waveguide multiplexer.

9. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising means for coupling optical signals from the single output waveguide into a single-mode optical fiber.

10. A method of multiplexing a plurality of optical signals of different wavelengths, comprising:

receiving, at each of a plurality of input waveguides formed in a silicon device layer of a silicon-on-insulator substrate, an optical signal at a respective wavelength;

guiding each optical signal through a respective tapered waveguide transition disposed between a respective input waveguide and a coupling region, wherein each tapered waveguide transition gradually varies a waveguide width to reduce insertion loss;

combining, in the coupling region, the plurality of optical signals of different wavelengths onto a single output waveguide formed in the silicon device layer;

wherein the combining achieves an insertion loss of less than approximately 1.5 dB per channel across a wavelength range of at least 35 nm.

11. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the waveguide multiplexer is integrated into an optical transceiver module for data-center interconnect applications, and wherein the single output waveguide is optically coupled to an output optical fiber.

12. The multi-channel silicon photonic waveguide multiplexer of claim 11, wherein the optical transceiver module is configured to operate as a 400G-ZR coherent transceiver module or an 800G-DR transceiver module in compliance with applicable industry-standard specifications.

13. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a cascaded arrangement of coupling stages, comprising:

a first plurality of coupling stages, each configured to combine a respective subset of the plurality of optical signals onto a respective intermediate waveguide; and

a second coupling stage configured to combine optical signals from the respective intermediate waveguides onto the single output waveguide;

wherein the cascaded arrangement enables multiplexing of 16 or more channels onto the single output waveguide.

14. A silicon photonic integrated circuit, comprising:

the multi-channel silicon photonic waveguide multiplexer of claim 1;

a plurality of optical modulators formed on the silicon-on-insulator substrate, each optical modulator coupled to a respective one of the plurality of input waveguides and configured to modulate an optical carrier signal at the respective wavelength with data;

at least one laser source optically coupled to the plurality of optical modulators and configured to provide optical carrier signals at the respective wavelengths; and

wherein the silicon photonic integrated circuit is configured for integration into an optical transceiver module for high-bandwidth data-center interconnect applications.

CERTIFICATE OF CORRECTION / REEXAMINATION HISTORY

No Certificate of Correction has been issued for U.S. Patent No. 10,234,847 B2 as of the date of this filing.

No ex parte reexamination or inter partes review (IPR) proceedings have been instituted before the United States Patent and Trademark Office with respect to this patent as of the date of this filing. Defendant Lumicore Technologies, Inc. has reserved its right to petition for inter partes review of the asserted claims under 35 U.S.C. § 311 et seq. The statutory deadline for filing an IPR petition under 35 U.S.C. § 315(b) — one year from the date the petitioner was served with a complaint alleging infringement — is May 1, 2025.

All maintenance fees required under 35 U.S.C. § 41 for U.S. Patent No. 10,234,847 B2 have been timely paid, and the patent remains in full force and effect.

ASSIGNMENT HISTORY / CHAIN OF TITLE

The following assignment history is recorded with the United States Patent and Trademark Office for U.S. Patent No. 10,234,847 B2:

U.S. Patent No. 10,234,847 B2 was originally filed by and assigned to Optiwave Semiconductor Corp., Santa Clara, California. The patent remains assigned to Optiwave Semiconductor Corp. No change in assignment has occurred.

Relationship to the '562 Patent (U.S. Patent No. 9,678,562). The '847 Patent is a continuation-in-part of Application No. 14/551,230, which issued as U.S. Patent No. 9,678,562 on June 13, 2017. The '562 Patent was originally filed by and assigned to Solara Optics, Inc. Optiwave Semiconductor Corp. acquired the '562 Patent, along with eleven other patents and patent applications (the "Solara IP Portfolio"), from Solara Optics, Inc. pursuant to an Asset Purchase Agreement dated June 15, 2018. The aggregate purchase price for the Solara IP Portfolio was $34.5 million. The assignment of the '562 Patent from Solara Optics, Inc. to Optiwave Semiconductor Corp. was recorded with the USPTO on July 2, 2018 at Reel/Frame 046352/0118.

It is important to note that while the '562 Patent was acquired from Solara Optics, the '847 Patent was filed by Optiwave Semiconductor Corp. itself on September 14, 2016, prior to the acquisition of the Solara IP Portfolio. The '847 Patent claims the benefit of priority through the continuation chain to the provisional application (Application No. 62/086,471) filed December 2, 2013. The continuation-in-part relationship between the '847 Patent and the '562 Patent establishes that these patents are in the same patent family, with interrelated prosecution histories relevant to claim construction and validity analyses for both patents.

CERTIFICATION

UNITED STATES PATENT AND TRADEMARK OFFICE

OFFICE OF PATENT LEGAL ADMINISTRATION

I hereby certify that the attached is a true and correct copy of United States Patent No. 10,234,847 B2, entitled "Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss," issued March 19, 2019, to inventor(s) Jian-Wei Huang, Nikolai Petrov, and Emily R. Vasquez, assigned to Optiwave Semiconductor Corp., as it appears in the records of the United States Patent and Trademark Office.

This certified copy comprises the patent's front page, specification, claims, drawings, and all associated data as recorded in the official patent file.

This certification is provided under the authority of the Director of the United States Patent and Trademark Office, pursuant to 37 C.F.R. § 1.14 and the provisions of 35 U.S.C. § 10.

UNITED STATES PATENT AND TRADEMARK OFFICE

By: ________

Certifying Officer Office of Patent Legal Administration

Date of Certification: April 15, 2024

[SEAL OF THE UNITED STATES PATENT AND TRADEMARK OFFICE]

RELEVANCE OF EXHIBIT A TO THE PRESENT LITIGATION

The following summary is provided by counsel for Plaintiff Optiwave Semiconductor Corp. for the convenience of the Court and does not form part of the certified patent document reproduced above.

U.S. Patent No. 10,234,847 (the "'847 Patent") is one of the patents-in-suit in this action and is central to Plaintiff Optiwave Semiconductor Corp.'s ("OWS") claims of patent infringement against Defendant Lumicore Technologies, Inc. ("Lumicore"). The following summarizes the key litigation touchpoints relevant to this patent:

Infringement. OWS asserts that Lumicore's LumiLink 400G-ZR+ optical transceiver module (commercially launched in Q3 2022; FY 2023 revenue of approximately $94.8 million) and LumiLink 800G-DR8 optical transceiver module (commercially launched in Q1 2023; FY 2023 revenue of approximately $128.4 million) infringe Claims 1, 3, 5, 9, and 14 of the '847 Patent. OWS's infringement contentions are supported by independent third-party teardown analyses conducted by Benchmark Semiconductor Analysis, LLC. The Benchmark teardown report for the LumiLink 400G-ZR+, dated December 12, 2022, and the Benchmark teardown report for the LumiLink 800G-DR8, dated June 2023, each confirmed the presence of waveguide multiplexer structures in the accused products that correspond to the claimed elements of the asserted claims. Detailed infringement claim charts mapping each limitation of each asserted claim to specific structures identified in the Benchmark teardown reports were served on Lumicore on September 16, 2024.

Claim Construction. The term "waveguide multiplexer" as used in independent Claim 1 of the '847 Patent is one of the fourteen (14) disputed claim terms identified in the parties' Joint Claim Construction Statement, filed on October 28, 2024. OWS proposes that "waveguide multiplexer" should be construed to mean "an optical device that combines multiple optical signals of different wavelengths onto a single waveguide." Lumicore proposes the narrower construction "an arrayed waveguide grating that combines optical signals using a slab coupler and phase-shifted waveguide array." OWS submits that the '847 Patent specification's discussion of multiple multiplexer architectures — including AWGs, MZI-based multiplexers, star couplers, and MMI couplers — in both the background and detailed description sections supports OWS's broader construction and forecloses Lumicore's attempt to limit the claim scope to a single embodiment. The Markman hearing on claim construction is scheduled for March 14, 2025 before the Honorable Judge James R. Gilstrap.

Additionally, Claim 9 contains the term "means for coupling optical signals from the single output waveguide into a single-mode optical fiber," which may invoke 35 U.S.C. § 112(f) (means-plus-function). The corresponding structure disclosed in the specification includes a grating coupler and an edge coupler with a spot-size converter, and equivalents thereof.

Lumicore has further argued in its claim construction briefing that independent Claim 1 should be narrowly construed in light of the additional limitations recited in dependent Claims 3 and 5. OWS has countered that the doctrine of claim differentiation precludes reading the narrower limitations of dependent claims into the broader independent claim.

Invalidity. Lumicore's invalidity contentions, served on October 14, 2024, cite six (6) prior-art references against the asserted claims of the '847 Patent. Lumicore's primary anticipation reference under 35 U.S.C. § 102 is Takahashi et al., "Low-Loss Silicon Photonic Waveguide Multiplexer with Sub-Decibel Insertion Loss," IEEE Photonics Technology Letters, Vol. 26, No. 6, pp. 601–604 (March 15, 2014). Lumicore further relies on PCT/EP2015/071234 (Simonsen, published September 17, 2015) in combination with other references for obviousness under 35 U.S.C. § 103. OWS notes that both Takahashi and Simonsen were before the Examiner during prosecution of the '847 Patent and were cited in the "References Cited" section of the issued patent, and therefore carry a presumption of validity under 35 U.S.C. § 282 that Lumicore must overcome by clear and convincing evidence.

Patent Family. The '847 Patent is in the same patent family as U.S. Patent No. 9,678,562 (the "'562 Patent"), with a continuation-in-part relationship. The '562 Patent is also asserted in this litigation. The prosecution histories of the two patents are interrelated and relevant to claim construction and validity analyses for both patents. The shared priority chain and overlapping prosecution history may bear on the construction of common claim terms and on the scope of prior-art defenses asserted by Lumicore.

IPR Deadline. Lumicore has reserved its right to petition for inter partes review of the asserted claims of the '847 Patent. The one-year statutory deadline under 35 U.S.C. § 315(b) for filing an IPR petition is May 1, 2025.

CERTIFICATE OF SERVICE: I hereby certify that on April 22, 2024, a true and correct copy of the foregoing Exhibit A was served on all counsel of record via the Court's CM/ECF electronic filing system.

CALDERWOOD & HARKNESS LLP

By: ________

Alan Ngo (CA Bar No. 246718) Attorneys for Plaintiff Optiwave Semiconductor Corp.

Date: April 22, 2024

OPTIWAVE SEMICONDUCTOR CORP.,

<!-- indent:1 -->Plaintiff,<!-- /indent -->	Case No. 2:24-cv-00319-JRG
v.	JUDGE JAMES R. GILSTRAP

LUMICORE TECHNOLOGIES, INC.,

<!-- indent:1 -->Defendant.<!-- /indent -->	JURY TRIAL DEMANDED
(12) United States Patent	(10) Patent No.: US 10,234,847 B2
Huang et al.	(45) Date of Patent: March 19, 2019
Patent No.	Date	Inventor(s)
7,068,885 B2	June 27, 2006	Doerr et al.
7,539,369 B2	May 26, 2009	Leuthold et al.
8,078,021 B2	December 13, 2011	Kobrinsky et al.
8,340,486 B2	December 25, 2012	Chen et al.
8,594,503 B2	November 26, 2013	Li et al.
8,768,124 B2	July 1, 2014	Mekis et al.
8,873,906 B2	October 28, 2014	Takahashi et al.
9,052,448 B2	June 9, 2015	Baehr-Jones et al.
9,110,232 B2	August 18, 2015	Hochberg et al.
9,195,001 B2	November 24, 2015	Vermeulen et al.
2014/0161385 A1	June 12, 2014	Okamoto
2015/0063745 A1	March 5, 2015	Song et al.
2016/0033721 A1	February 4, 2016	Fang et al.
Publication No.	Country	Date
EP 2 856 215 A1	EP	April 8, 2015
WO 2013/152288 A1	WO	October 10, 2013
WO 2014/089454 A2	WO	June 12, 2014
PCT/EP2015/071234	WO	September 17, 2015
CN 104765099 A	CN	July 8, 2015
Reel/Frame	Date Recorded	Assignor	Assignee	Description
039812/0450	September 14, 2016	Jian-Wei Huang; Nikolai Petrov; Emily R. Vasquez	Optiwave Semiconductor Corp.	Assignment of Application No. 15/265,418 at filing

EXHIBIT A
UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION
CERTIFIED COPY OF U.S. PATENT NO. 10,234,847
"Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss"
Filed as Exhibit A to Plaintiff's Original Complaint
Filed: April 22, 2024
Attorneys for Plaintiff Optiwave Semiconductor Corp.:
CALDERWOOD & HARKNESS LLP
Alan Ngo, Responsible Partner (CA Bar No. 246718) Marcus Delgado, Billing Partner (CA Bar No. 289543) 350 South Grand Avenue, 48th Floor Los Angeles, California 90071 Telephone: (213) 555-7200 Facsimile: (213) 555-7201
Email: ango@calderwoodharkness.com
Email: mdelgado@calderwoodharkness.com
Local Counsel:
WHITMORE & CALLAHAN LLP
James "Jim" Callahan (TX Bar No. 03891247) 110 North College Avenue, Suite 800 Tyler, Texas 75702 Telephone: (903) 555-1400 Facsimile: (903) 555-1401
Email: jcallahan@whitmorecallahan.com
UNITED STATES PATENT
US 10,234,847 B2
(54) MULTI-CHANNEL SILICON PHOTONIC WAVEGUIDE MULTIPLEXER WITH LOW INSERTION LOSS
(75) Inventors:
Jian-Wei Huang, Santa Clara, CA (US); Nikolai Petrov, Santa Clara, CA (US); Emily R. Vasquez, Sunnyvale, CA (US)
(73) Assignee: Optiwave Semiconductor Corp., Santa Clara, CA (US)
(  ) Notice:* Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. § 154(b) by 0 days.
(21) Appl. No.: 15/265,418
(22) Filed: September 14, 2016
(65) Prior Publication Data
US 2017/0082808 A1 — March 23, 2017
Related U.S. Application Data
(63) Continuation-in-part of application No. 14/551,230, filed on November 22, 2014, now U.S. Pat. No. 9,678,562, issued June 13, 2017.
(60) Provisional application No. 62/086,471, filed on December 2, 2013.
(51) Int. Cl.
G02B 6/12 (2006.01) G02B 6/293 (2006.01) H04J 14/02 (2006.01)
(52) U.S. Cl.
CPC — G02B 6/12007 (2013.01); G02B 6/29344 (2013.01); H04J 14/0201 (2013.01); G02B 6/12004 (2013.01); G02B 6/29361 (2013.01)
(58) Field of Classification Search
CPC — G02B 6/12007; G02B 6/12004; G02B 6/29344; G02B 6/29361; H04J 14/0201; H04J 14/0208 USPC — 385/24, 37, 39, 46, 129, 130, 131; 398/79, 82, 83, 87 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
FOREIGN PATENT DOCUMENTS
OTHER PUBLICATIONS
Takahashi, H. et al., "Low-Loss Silicon Photonic Waveguide Multiplexer with Sub-Decibel Insertion Loss," IEEE Photonics Technology Letters, Vol. 26, No. 6, pp. 601–604, March 15, 2014.
Bogaerts, W. et al., "Silicon microring resonators," Tidewater Group, Vol. 6, No. 1, pp. 47–73, 2012.
Pathak, S. et al., "Comparison of AWGs and Echelle Gratings for Wavelength Division Multiplexing on Silicon-on-Insulator," IEEE Photonics Journal, Vol. 6, No. 5, pp. 1–9, October 2014.
Doerr, C.R. et al., "Silicon photonics broadband modulation-based isolator," Optics Express, Vol. 22, No. 4, pp. 4493–4498, 2014.
Thomson, D. et al., "Roadmap on silicon photonics," Journal of Optics, Vol. 18, No. 7, 073003, 2016.
Cheben, P. et al., "Subwavelength integrated photonics," Nature, Vol. 560, pp. 565–572, 2018 (cited by applicant during prosecution).
(74) Attorney, Agent, or Firm — Cascade IP Advisors, LLC; Dr. Martin Chu, Lead Prosecution Attorney; 1550 Crystal Drive, Suite 600, Arlington, VA 22202
(57) ABSTRACT
A multi-channel silicon photonic waveguide multiplexer is disclosed that combines multiple optical signals of different wavelengths onto a single output waveguide with low insertion loss. The multiplexer is fabricated on a silicon-on-insulator (SOI) substrate using standard CMOS-compatible semiconductor fabrication processes. The device employs a novel waveguide geometry and coupling arrangement that achieves insertion loss below approximately 1.5 dB per channel across the C-band (1530–1565 nm) and L-band (1565–1625 nm) wavelength ranges. The multiplexer utilizes tapered waveguide transitions and mode-matching structures at the coupling region to minimize modal mismatch and reduce scattering losses. The multiplexer is suitable for integration into optical transceiver modules for data-center interconnect applications, supporting dense wavelength-division multiplexing (DWDM) with channel counts of 4, 8, or 16 channels. The device is scalable through a cascaded coupling-stage architecture and is compatible with high-volume semiconductor manufacturing processes.
9 Drawing Sheets 14 Claims
DRAWINGS
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a multi-channel silicon photonic waveguide multiplexer in accordance with an embodiment of the present invention, showing a plurality of input waveguides (102a–102h), a coupling region (104), and a single output waveguide (106), illustrating the general architecture of the multiplexer device.
FIG. 2 is a cross-sectional view of the silicon-on-insulator (SOI) waveguide structure employed in the multiplexer of FIG. 1, taken along the line A-A′, showing the silicon core (202), the buried oxide (Box) layer (204), the silicon handle wafer (206), and the upper cladding layer (208), with dimensions of the waveguide core annotated in nanometers.
FIG. 3 is a top-view layout of an 8-channel waveguide multiplexer embodiment in accordance with the present invention, showing the arrangement of input ports (302a–302h), waveguide routing paths (304), the coupling region (306), and the output port (308).
FIG. 4 is a detailed view of the coupling region (104) of the waveguide multiplexer of FIG. 1, illustrating the tapered waveguide transitions (402) and mode-matching structures (404) that reduce insertion loss at the interface between the input waveguides and the coupling region.
FIG. 5 is a graph plotting measured insertion loss in decibels (dB) versus wavelength in nanometers (nm) across the C-band (1530–1565 nm) for each of the 8 channels (Ch. 1 through Ch. 8) of the waveguide multiplexer embodiment of FIG. 3, demonstrating that insertion loss remains below 1.5 dB per channel across the measured wavelength range.
FIG. 6 is a graph plotting channel crosstalk in decibels (dB) versus wavelength in nanometers (nm) for the 8-channel embodiment of FIG. 3, showing adjacent-channel crosstalk levels below −25 dB across the C-band wavelength range.
FIG. 7 is a schematic diagram of an optical transceiver module incorporating the waveguide multiplexer of the present invention, showing integration of the multiplexer (702) with laser sources (704), optical modulators (706), and photodetectors (708) on a silicon photonic integrated circuit (PIC) (710).
FIG. 8 is a top-view layout of an alternative embodiment of the present invention, showing a 16-channel waveguide multiplexer (800) with a cascaded arrangement of coupling stages (802a, 802b) for multiplexing 16 input channels onto a single output waveguide.
FIG. 9 is a block diagram of a system-level embodiment showing the waveguide multiplexer (902) of the present invention integrated into a data-center interconnect link, with a transmitter module (904) and a receiver module (906) connected via a single-mode fiber (908), illustrating the end-to-end optical communication architecture.
[Note: Figures are not reproduced in this text version. Reference is made to the original patent document as filed with the USPTO, which includes nine sheets of drawings corresponding to FIGS. 1–9 described above.]
SPECIFICATION
MULTI-CHANNEL SILICON PHOTONIC WAVEGUIDE MULTIPLEXER WITH LOW INSERTION LOSS
FIELD OF THE INVENTION
The present invention relates generally to silicon photonic devices, and more particularly to multi-channel waveguide multiplexers for combining multiple wavelength channels onto a single optical waveguide with low insertion loss. The invention is directed to devices suitable for use in optical transceiver modules and data-center interconnect applications employing dense wavelength-division multiplexing (DWDM) techniques. The invention further relates to silicon-on-insulator (SOI) based photonic integrated circuits (PICs) and methods for fabricating waveguide multiplexer structures using CMOS-compatible semiconductor manufacturing processes.
BACKGROUND OF THE INVENTION
The explosive growth of cloud computing, artificial intelligence workloads, and streaming media services has driven unprecedented demand for high-bandwidth optical interconnects within and between hyperscale data centers. Modern hyperscale data centers operated by major cloud service providers require interconnect solutions capable of supporting data rates of 400 Gbps, 800 Gbps, and beyond over distances ranging from intra-rack connections of a few meters to campus-scale links spanning tens of kilometers. Silicon photonics has emerged as a leading platform for implementing these high-bandwidth optical interconnect solutions due to the technology's compatibility with established CMOS semiconductor manufacturing infrastructure, which enables high-volume production at significantly lower cost per device than competing photonic platforms based on indium phosphide (InP) or other III-V compound semiconductor materials.
A critical component in high-bandwidth optical interconnect systems is the wavelength-division multiplexer, which combines multiple optical signals at different wavelengths onto a single optical fiber or waveguide. The multiplexer reduces the number of physical fibers required for a given aggregate bandwidth by allowing multiple data channels to share a single fiber, with each channel operating at a distinct wavelength within the optical transmission window. Dense wavelength-division multiplexing (DWDM) systems operating in the C-band (approximately 1530 to 1565 nm) and L-band (approximately 1565 to 1625 nm) can support 8, 16, 32, or more channels on a single fiber, with channel spacings as narrow as 100 GHz or less.
Several approaches to implementing waveguide multiplexers on silicon photonic platforms have been reported in the prior art. Arrayed waveguide gratings (AWGs) represent one widely studied approach. An AWG consists of a set of input waveguides coupled to a first slab coupler (also referred to as a free propagation region), an array of waveguides with carefully controlled path-length differences (the phased array), a second slab coupler, and a set of output waveguides. The operation of an AWG relies on the constructive and destructive interference of optical signals propagating through the phased array to achieve wavelength-selective routing of individual channels to designated output ports. While AWGs can achieve high channel counts, they are subject to significant insertion loss, particularly when fabricated on silicon-on-insulator platforms where the high index contrast between the silicon core and the silicon dioxide cladding amplifies the effects of waveguide sidewall roughness and dimensional variations. Typical insertion losses for silicon-based AWGs reported in the literature range from 2 dB to 5 dB or more per channel, which is unacceptable for many high-performance transceiver applications.
Echelle gratings, also known as planar concave gratings, represent an alternative approach to wavelength-division multiplexing on silicon platforms. Echelle gratings use a single reflecting surface with a periodic corrugation to diffract different wavelengths to different spatial locations, where they are collected by output waveguides. While echelle gratings can be compact and are capable of supporting a moderate number of channels, they are sensitive to fabrication variations in the grating facet profile and tend to exhibit higher insertion loss and poorer crosstalk performance than AWGs when implemented in high-index-contrast silicon waveguide platforms.
Mach-Zehnder interferometer (MZI) based multiplexers represent a third approach, in which cascaded stages of MZI filters are used to separate or combine wavelength channels. MZI-based multiplexers offer the advantage of relatively simple design and good spectral flatness within each channel passband, but the cascaded architecture results in a device that grows in size and complexity with increasing channel count, and the cumulative insertion loss of multiple MZI stages can be substantial.
Each of these existing approaches suffers from one or more significant limitations when implemented on silicon-on-insulator platforms for high-volume manufacturing. High insertion loss degrades the power budget of the optical link, reducing the maximum achievable transmission distance or requiring the use of higher-power laser sources that increase cost and power consumption. Manufacturing variability inherent in CMOS fabrication processes introduces channel-to-channel non-uniformity in insertion loss and center wavelength, reducing yield and necessitating costly post-fabrication trimming or calibration procedures. Limited channel count restricts the aggregate bandwidth that can be supported on a single fiber, requiring additional fibers and associated optical connectors that increase system cost and complexity.
There is therefore a need in the art for a CMOS-compatible waveguide multiplexer that achieves low insertion loss across a broad wavelength range while supporting high channel counts, and that is suitable for integration into high-volume silicon photonic transceiver modules for data-center interconnect and telecommunications applications.
SUMMARY OF THE INVENTION
The present invention provides a multi-channel silicon photonic waveguide multiplexer fabricated on a silicon-on-insulator (SOI) substrate that addresses the limitations of existing waveguide multiplexer designs. The waveguide multiplexer of the present invention combines multiple optical signals of different wavelengths onto a single output waveguide with insertion loss below approximately 1.5 dB per channel across a wavelength range spanning at least the C-band (1530–1565 nm).
In accordance with one aspect of the invention, the waveguide multiplexer comprises a plurality of input waveguides, each configured to receive an optical signal at a respective wavelength, and a coupling region configured to combine the optical signals from the plurality of input waveguides onto a single output waveguide. Tapered waveguide transitions are disposed between the input waveguides and the coupling region and are configured to provide adiabatic mode conversion that reduces insertion loss at the interface between the input waveguides and the coupling region. The tapered waveguide transitions achieve mode matching between the narrower input waveguides and the wider waveguide structures within the coupling region, thereby minimizing modal mismatch loss and reducing back-reflection.
In accordance with another aspect of the invention, mode-matching structures are provided within the coupling region that further reduce insertion loss by ensuring efficient power transfer between the input modes and the output mode of the output waveguide. The mode-matching structures may include tapered slab regions, multimode interference (MMI) couplers, or other structures configured to minimize scattering and radiation losses at waveguide junctions.
The waveguide multiplexer of the present invention is scalable to support channel counts of 4, 8, or 16 channels, with optimized channel spacing of approximately 200 GHz or 400 GHz for compatibility with standard DWDM wavelength grids. For channel counts exceeding 8, the multiplexer may employ a cascaded arrangement of coupling stages, wherein a first set of coupling stages combines groups of input channels and a second coupling stage combines the outputs of the first set of coupling stages onto the single output waveguide.
The waveguide multiplexer is fabricated using semiconductor fabrication processes that are fully compatible with standard CMOS foundry manufacturing, including photolithographic patterning, reactive ion etching, chemical vapor deposition, and chemical mechanical planarization. This compatibility enables high-volume manufacturing of the waveguide multiplexer at established CMOS foundries, achieving economies of scale and cost structures that are not attainable with photonic devices fabricated on non-silicon platforms.
The waveguide multiplexer of the present invention is particularly suitable for integration into optical transceiver modules for data-center interconnect applications, including 400G-ZR, 400G-DR4, 800G-DR8, and other standardized transceiver form factors. The waveguide multiplexer may be monolithically integrated with other silicon photonic components, including laser sources, optical modulators, photodetectors, and electronic driver and receiver circuits, on a single silicon photonic integrated circuit (PIC).
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The following detailed description sets forth specific embodiments of the present invention with reference to the accompanying drawings. The description is not intended to limit the scope of the invention, which is defined by the appended claims. Those skilled in the art will recognize that various modifications and alternative implementations are possible without departing from the spirit and scope of the invention as defined by the claims.
1. Waveguide Structure
Referring now to FIG. 2, the waveguide multiplexer of the present invention is fabricated on a silicon-on-insulator (SOI) platform. The SOI substrate comprises a silicon handle wafer 206, a buried oxide (Box) layer 204 disposed on the silicon handle wafer 206, and a silicon device layer disposed on the box layer 204. The silicon device layer is patterned to form the silicon core 202 of the optical waveguides. An upper cladding layer 208, which may comprise silicon dioxide (SiO₂) deposited by plasma-enhanced chemical vapor deposition (PECVD) or other suitable deposition technique, is disposed over the patterned silicon core 202.
In a preferred embodiment, the silicon core 202 has a thickness of approximately 220 nm and a width that varies depending on the specific waveguide function. For single-mode operation at C-band wavelengths, the waveguide width is approximately 450 nm to 500 nm. The box layer 204 has a thickness of approximately 2 µm to 3 µm, which provides sufficient optical isolation from the silicon handle wafer 206 to prevent leakage of the guided optical mode into the substrate. The upper cladding layer 208 has a thickness of approximately 1.5 µm to 3 µm.
The waveguide dimensions are selected to ensure single-mode operation for the transverse-electric (TE) polarization at wavelengths within the C-band and L-band. The high index contrast between the silicon core (refractive index approximately 3.48 at 1550 nm) and the silicon dioxide cladding (refractive index approximately 1.44 at 1550 nm) provides strong optical confinement, enabling tight waveguide bends with radii as small as 5 µm with acceptable radiation loss. However, the high index contrast also amplifies the effects of waveguide sidewall roughness on scattering loss. The present invention addresses this challenge through specific design features described in the sections below.
The waveguide structures are fabricated using standard CMOS-compatible semiconductor fabrication processes. The silicon device layer is patterned using deep-ultraviolet (DUV) photolithography with 193 nm or 248 nm illumination, followed by reactive ion etching (RIE) to define the waveguide core. The etch process is optimized to achieve smooth sidewall profiles with root-mean-square (RMS) roughness below approximately 2 nm, which minimizes scattering loss. The upper cladding layer is deposited by PECVD and planarized by chemical mechanical planarization (CMP) to provide a smooth surface for subsequent processing steps or for flip-chip bonding of laser die.
In alternative embodiments, the upper cladding layer 208 may comprise silicon nitride (Si₃N₄) or a combination of silicon dioxide and silicon nitride layers. Silicon nitride cladding offers a lower index contrast with the silicon core compared to silicon dioxide cladding, which can reduce scattering sensitivity to sidewall roughness in certain waveguide geometries. The selection of cladding material may be optimized based on the specific requirements of the multiplexer design and the available fabrication process at the target CMOS foundry.
2. Multiplexer Architecture
Referring now to FIG. 1 and FIG. 3, the waveguide multiplexer 100 of the present invention comprises a plurality of input waveguides 102a–102h, a coupling region 104, and a single output waveguide 106. In the 8-channel embodiment illustrated in FIG. 3, eight input waveguides 302a–302h are routed from input ports 302a–302h at the periphery of the photonic integrated circuit to the coupling region 306, where the optical signals carried by the eight input waveguides are combined onto the single output waveguide leading to output port 308.
Each input waveguide 102a–102h is configured to receive an optical signal at a respective wavelength λ₁ through λ₈, where the wavelengths are assigned according to a standard DWDM wavelength grid. In a preferred embodiment, the channel spacing is approximately 200 GHz (approximately 1.6 nm at 1550 nm center wavelength), providing compatibility with ITU-T G.694.1 DWDM wavelength grids. In an alternative embodiment, the channel spacing is approximately 400 GHz (approximately 3.2 nm), which may be preferred in applications where reduced channel count or wider passband is acceptable.
The coupling region 104 is the portion of the multiplexer where the optical signals from the plurality of input waveguides are combined onto the single output waveguide 106. The present invention is not limited to a specific coupling architecture within the coupling region. In one embodiment, the coupling region employs an arrayed waveguide grating (AWG) architecture comprising a first slab coupler, a phased array of waveguides with controlled path-length differences, and a second slab coupler. In another embodiment, the coupling region employs a cascaded Mach-Zehnder interferometer (MZI) architecture. In yet another embodiment, the coupling region employs a star coupler or multimode interference (MMI) coupler architecture. The selection of coupling architecture may be based on the specific requirements of the application, including channel count, channel spacing, passband shape, and die area constraints.
Regardless of the specific coupling architecture employed within the coupling region, the waveguide multiplexer of the present invention includes tapered waveguide transitions and mode-matching structures at the interfaces between the input waveguides and the coupling region, as described in detail below with reference to FIG. 4. These interface structures are a key innovation of the present invention and are responsible for achieving the low insertion loss performance that distinguishes the present invention from prior-art waveguide multiplexers.
The waveguide routing paths 304 between the input ports and the coupling region are designed with optimized bend radii to minimize radiation loss at waveguide bends. In a preferred embodiment, the minimum bend radius is approximately 10 µm, which provides a radiation loss below 0.01 dB per 90-degree bend for the TE fundamental mode at C-band wavelengths. The waveguide routing paths are arranged to minimize crossings between waveguides, and where crossings are unavoidable, the crossings are implemented using waveguide intersection designs that minimize crosstalk and insertion loss.
3. Low Insertion Loss Design
Referring now to FIG. 4, the waveguide multiplexer of the present invention achieves low insertion loss through several specific design features that collectively reduce the dominant loss mechanisms in silicon photonic waveguide multiplexers.
Adiabatic Tapers. Tapered waveguide transitions 402 are disposed at the interfaces between the input waveguides 102a–102h and the coupling region 104. Each tapered waveguide transition 402 comprises an adiabatic taper in which the waveguide width is gradually varied from the width of the input waveguide (e.g., approximately 450 nm) to the width required at the entrance to the coupling region (e.g., approximately 1.5 µm to 3 µm, depending on the coupling architecture). The taper profile is designed to be adiabatic, meaning that the rate of change of the waveguide width is sufficiently gradual that substantially all optical power remains in the fundamental guided mode throughout the transition, with negligible excitation of higher-order modes or radiation modes. In a preferred embodiment, the taper length is at least 50 µm, and more preferably at least 100 µm, to ensure adiabatic operation across the full C-band wavelength range. The taper profile may be linear, parabolic, exponential, or a combination thereof, optimized to minimize insertion loss for a given taper length.
Mode-Matching Structures. Mode-matching structures 404 are provided within the coupling region 104 at the junctions between the tapered waveguide transitions 402 and the internal structures of the coupling region (e.g., the slab coupler in an AWG embodiment, or the input ports of an MMI coupler). The mode-matching structures 404 are configured to minimize modal mismatch between the guided mode at the output of the tapered waveguide transition and the mode of the coupling region structure. In one embodiment, the mode-matching structures comprise short sections of waveguide with intermediate dimensions that provide a stepped transition between the taper output and the coupling region. In another embodiment, the mode-matching structures comprise tapered slab regions that gradually transition from a channel waveguide geometry to a slab waveguide geometry. The mode-matching structures reduce the fraction of optical power that is scattered into radiation modes at the junction, thereby reducing insertion loss.
Optimized Bend Radii. All waveguide bends in the multiplexer are designed with radii optimized to balance radiation loss and device footprint. In the preferred embodiment, the minimum bend radius is 10 µm for standard single-mode waveguides and 20 µm for wider multimode waveguides in the coupling region. These bend radii provide radiation losses below 0.01 dB per bend at C-band wavelengths.
Reduced Sidewall Scattering Loss. The waveguide structures in the multiplexer are fabricated using an optimized etch process that achieves sidewall RMS roughness below 2 nm. Additionally, the waveguide width in the coupling region and in the phased-array waveguides (in the AWG embodiment) is wider than the minimum single-mode width, which reduces the overlap of the guided mode with the rough sidewalls and thereby reduces scattering loss per unit length. The combination of smooth sidewalls and reduced mode-sidewall overlap results in propagation loss below 1 dB/cm in the multiplexer waveguides.
Referring now to FIG. 5, the measured insertion loss of the 8-channel waveguide multiplexer embodiment of FIG. 3 is plotted as a function of wavelength across the C-band for each of the 8 channels. The measured data demonstrates that insertion loss remains below 1.5 dB per channel for all 8 channels across the wavelength range from 1530 nm to 1565 nm. The minimum insertion loss is approximately 0.8 dB, observed for the center channels (Ch. 4 and Ch. 5), while the edge channels (Ch. 1 and Ch. 8) exhibit slightly higher insertion loss of approximately 1.3 dB due to increased slab-diffraction loss at the extremes of the wavelength range. These results represent a significant improvement over prior-art silicon photonic AWGs, which typically exhibit insertion losses of 2 dB to 5 dB per channel.
Referring now to FIG. 6, the measured crosstalk performance of the 8-channel embodiment is plotted as a function of wavelength. The adjacent-channel crosstalk is below −25 dB for all channels across the C-band, and the non-adjacent-channel crosstalk is below −35 dB. These crosstalk levels meet the requirements of standard DWDM transceiver specifications, including OIF 400ZR and IEEE 802.3 standards.
4. Integration into Transceiver Modules
Referring now to FIG. 7, the waveguide multiplexer of the present invention is designed for monolithic or hybrid integration into silicon photonic transceiver modules for data-center interconnect applications. In the embodiment illustrated in FIG. 7, the waveguide multiplexer 702 is integrated onto a silicon photonic integrated circuit (PIC) 710 along with a plurality of optical modulators 706, at least one laser source 704, and a plurality of photodetectors 708.
The laser source 704 may comprise a distributed feedback (DFB) laser or an external cavity laser that is bonded to the PIC using flip-chip bonding, wafer-level bonding, or other hybrid integration techniques. In an alternative embodiment, the laser source may be integrated monolithically on the SOI platform using heterogeneous integration of III-V gain materials. The laser source provides a multi-wavelength optical carrier that is distributed to the plurality of optical modulators via a network of waveguide splitters or, in certain embodiments, via a comb laser source that generates multiple wavelength tones simultaneously.
The optical modulators 706 may comprise Mach-Zehnder modulators (MZMs), ring modulators, or electro-absorption modulators (EAMs), each configured to encode data onto the optical carrier at the respective wavelength. The modulated optical signals from the modulators are routed via the input waveguides to the waveguide multiplexer 702, which combines the modulated signals onto the single output waveguide for coupling to an output fiber.
On the receiver side, a corresponding waveguide demultiplexer (which may have the same architecture as the multiplexer, operated in reverse) separates the received wavelength channels, and the individual channel signals are directed to the photodetectors 708 for optical-to-electrical conversion. The photodetectors may comprise germanium (Ge) photodiodes monolithically integrated on the SOI platform.
The silicon photonic integrated circuit 710 may be packaged as a pluggable transceiver module in standard form factors, including QSFP-DD, OSFP, and CFP2-DCO, for deployment in data-center switches and routers. The transceiver module may comply with industry-standard specifications including OIF 400ZR, Open ROADM, IEEE 802.3bs (400GBASE-DR4), and IEEE 802.3ck (800GBASE-DR8), among others.
The waveguide multiplexer architecture of the present invention is particularly well-suited for integration into next-generation transceiver module configurations operating at aggregate data rates of 400 Gbps, 800 Gbps, and 1.6 Tbps. In a 400G-ZR transceiver module, the multiplexer combines four modulated wavelength channels, each carrying 100 Gbps, onto a single output fiber. In an 800G-DR transceiver module, the multiplexer combines eight modulated wavelength channels, each carrying 100 Gbps, onto a single output fiber. In future 1.6 Tbps transceiver modules, the multiplexer combines sixteen modulated wavelength channels using the cascaded coupling stage architecture described below.
5. Alternative Embodiments
4-Channel Configuration. In a first alternative embodiment, the waveguide multiplexer comprises four input waveguides and is configured to combine four wavelength channels onto a single output waveguide. The 4-channel configuration is suitable for 400G-DR4 transceiver modules and other lower-bandwidth applications where a reduced channel count is sufficient. The 4-channel configuration offers reduced die area and simplified waveguide routing compared to the 8-channel embodiment.
16-Channel Cascaded Configuration. Referring now to FIG. 8, in a second alternative embodiment, the waveguide multiplexer 800 comprises sixteen input waveguides and employs a cascaded arrangement of coupling stages 802a, 802b for multiplexing sixteen input channels onto a single output waveguide. In this embodiment, a first set of coupling stages 802a comprises two 8-channel multiplexers, each combining eight input channels onto a respective intermediate waveguide. A second coupling stage 802b combines the two intermediate waveguides onto the single output waveguide. The cascaded architecture enables scaling to 16 or more channels while maintaining the low insertion loss performance of each individual coupling stage. The total insertion loss of the 16-channel cascaded multiplexer is the sum of the insertion loss of the 8-channel stage (less than 1.5 dB) and the insertion loss of the 2-channel combining stage (less than 0.5 dB), resulting in a total insertion loss below approximately 2.0 dB per channel.
Silicon Nitride Cladding Variations. In a third alternative embodiment, the upper cladding layer comprises silicon nitride (Si₃N₄) rather than silicon dioxide. The lower index contrast between silicon and silicon nitride, compared to silicon and silicon dioxide, reduces the sensitivity of the multiplexer performance to waveguide sidewall roughness and dimensional variations. This embodiment may be preferred for applications requiring the tightest possible insertion loss specifications.
System-Level Embodiment. Referring now to FIG. 9, in a system-level embodiment, the waveguide multiplexer 902 of the present invention is integrated into a data-center interconnect link comprising a transmitter module 904 and a receiver module 906 connected via a single-mode fiber 908. The transmitter module 904 comprises the waveguide multiplexer 902 together with laser sources, modulators, and electronic driver circuits. The receiver module 906 comprises a corresponding waveguide demultiplexer together with photodetectors and transimpedance amplifier (TIA) circuits. The single-mode fiber 908 may have a length ranging from 500 meters to 120 kilometers, depending on the transceiver specification. The low insertion loss of the waveguide multiplexer 902 contributes directly to the link power budget, enabling longer transmission distances or reduced laser power consumption compared to systems employing prior-art waveguide multiplexers with higher insertion loss.
6. Relationship to Thermal Management
The performance of silicon photonic waveguide multiplexers is sensitive to temperature variations due to the thermo-optic coefficient of silicon (approximately 1.86 × 10⁻⁴ /°C at 1550 nm). Temperature changes shift the center wavelength of each channel in the multiplexer, which can degrade insertion loss and crosstalk performance if the channel wavelengths shift outside the passband. The waveguide multiplexer of the present invention is designed to operate over a temperature range of 0°C to 70°C with the aid of appropriate thermal management solutions.
Thermal management solutions for the waveguide multiplexer are described in detail in related U.S. Patent No. 9,678,562 (the '562 Patent), entitled "Method for Thermal Management of Photonic Integrated Circuits Using Embedded Micro-Channel Heat Sinks," filed November 22, 2014, issued June 13, 2017, which is a parent application of the present application and is hereby incorporated by reference in its entirety. The '562 Patent discloses embedded micro-channel heat sinks that provide localized temperature control of the photonic integrated circuit, enabling the waveguide multiplexer to maintain stable channel wavelengths over the required operating temperature range. The thermal management techniques disclosed in the '562 Patent are complementary to the waveguide multiplexer design disclosed in the present application, and the two inventions may be implemented together on a single silicon photonic integrated circuit to provide a complete multiplexer solution with integrated thermal management.
The present application is a continuation-in-part of the application that issued as the '562 Patent, and claims priority through this continuation chain to the provisional application filed December 2, 2013.
INDUSTRIAL APPLICABILITY
The multi-channel silicon photonic waveguide multiplexer of the present invention is applicable to a wide range of optical communication applications, including without limitation: hyperscale data-center interconnects operating at aggregate data rates of 400 Gbps, 800 Gbps, 1.6 Tbps, and beyond; metropolitan-area telecom networks employing DWDM technology; long-haul fiber-optic communication systems; campus-scale optical interconnects; and high-performance computing cluster interconnects. The CMOS-compatible fabrication process enables high-volume manufacturing at established semiconductor foundries, providing a cost-effective solution for mass-market deployment of silicon photonic transceiver modules.
CLAIMS
What is claimed is:
1. A multi-channel silicon photonic waveguide multiplexer, comprising:
a silicon-on-insulator substrate comprising a silicon device layer disposed on a buried oxide layer;
a plurality of input waveguides formed in the silicon device layer, each input waveguide configured to receive an optical signal at a respective wavelength;
a coupling region configured to combine the plurality of optical signals of different wavelengths from the plurality of input waveguides onto a single output waveguide formed in the silicon device layer;
a plurality of tapered waveguide transitions disposed between the plurality of input waveguides and the coupling region, each tapered waveguide transition configured to gradually vary a waveguide width from a width of a respective input waveguide to a width at an entrance to the coupling region, wherein the tapered waveguide transitions reduce insertion loss at the interface between the input waveguides and the coupling region;
wherein the waveguide multiplexer achieves an insertion loss of less than approximately 1.5 dB per channel across a wavelength range of at least 35 nm; and
wherein the waveguide multiplexer is fabricated using semiconductor fabrication processes compatible with complementary metal-oxide-semiconductor (CMOS) manufacturing.
2. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the plurality of input waveguides comprises at least 8 input waveguides, each configured to receive an optical signal at a respective one of at least 8 different wavelengths.
3. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a mode-matching structure disposed in the coupling region and configured to minimize modal mismatch between the plurality of input waveguides and the single output waveguide, wherein the mode-matching structure comprises at least one of a tapered slab region, a multimode interference coupler section, or a stepped waveguide transition configured to provide a gradual transition between a channel waveguide geometry and a slab waveguide geometry within the coupling region.
4. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein a channel spacing between adjacent ones of the respective wavelengths is approximately 200 GHz or approximately 400 GHz, corresponding to a standard dense wavelength-division multiplexing (DWDM) wavelength grid.
5. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein each of the plurality of tapered waveguide transitions comprises an adiabatic taper having a taper length of at least 50 µm, the adiabatic taper configured such that substantially all optical power remains in a fundamental guided mode throughout the tapered waveguide transition.
6. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the silicon device layer of the silicon-on-insulator substrate has a thickness of between 200 nm and 300 nm.
7. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the waveguide multiplexer achieves an insertion loss of less than approximately 1.0 dB per channel across the wavelength range of at least 35 nm.
8. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a wavelength-tuning element operably coupled to at least one of the plurality of input waveguides or to the coupling region, the wavelength-tuning element configured to adjust a center wavelength of at least one channel of the waveguide multiplexer.
9. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising means for coupling optical signals from the single output waveguide into a single-mode optical fiber.
10. A method of multiplexing a plurality of optical signals of different wavelengths, comprising:
receiving, at each of a plurality of input waveguides formed in a silicon device layer of a silicon-on-insulator substrate, an optical signal at a respective wavelength;
guiding each optical signal through a respective tapered waveguide transition disposed between a respective input waveguide and a coupling region, wherein each tapered waveguide transition gradually varies a waveguide width to reduce insertion loss;
combining, in the coupling region, the plurality of optical signals of different wavelengths onto a single output waveguide formed in the silicon device layer;
wherein the combining achieves an insertion loss of less than approximately 1.5 dB per channel across a wavelength range of at least 35 nm.
11. The multi-channel silicon photonic waveguide multiplexer of claim 1, wherein the waveguide multiplexer is integrated into an optical transceiver module for data-center interconnect applications, and wherein the single output waveguide is optically coupled to an output optical fiber.
12. The multi-channel silicon photonic waveguide multiplexer of claim 11, wherein the optical transceiver module is configured to operate as a 400G-ZR coherent transceiver module or an 800G-DR transceiver module in compliance with applicable industry-standard specifications.
13. The multi-channel silicon photonic waveguide multiplexer of claim 1, further comprising a cascaded arrangement of coupling stages, comprising:
a first plurality of coupling stages, each configured to combine a respective subset of the plurality of optical signals onto a respective intermediate waveguide; and
a second coupling stage configured to combine optical signals from the respective intermediate waveguides onto the single output waveguide;
wherein the cascaded arrangement enables multiplexing of 16 or more channels onto the single output waveguide.
14. A silicon photonic integrated circuit, comprising:
the multi-channel silicon photonic waveguide multiplexer of claim 1;
a plurality of optical modulators formed on the silicon-on-insulator substrate, each optical modulator coupled to a respective one of the plurality of input waveguides and configured to modulate an optical carrier signal at the respective wavelength with data;
at least one laser source optically coupled to the plurality of optical modulators and configured to provide optical carrier signals at the respective wavelengths; and
wherein the silicon photonic integrated circuit is configured for integration into an optical transceiver module for high-bandwidth data-center interconnect applications.
CERTIFICATE OF CORRECTION / REEXAMINATION HISTORY
No Certificate of Correction has been issued for U.S. Patent No. 10,234,847 B2 as of the date of this filing.
No ex parte reexamination or inter partes review (IPR) proceedings have been instituted before the United States Patent and Trademark Office with respect to this patent as of the date of this filing. Defendant Lumicore Technologies, Inc. has reserved its right to petition for inter partes review of the asserted claims under 35 U.S.C. § 311 et seq. The statutory deadline for filing an IPR petition under 35 U.S.C. § 315(b) — one year from the date the petitioner was served with a complaint alleging infringement — is May 1, 2025.
All maintenance fees required under 35 U.S.C. § 41 for U.S. Patent No. 10,234,847 B2 have been timely paid, and the patent remains in full force and effect.
ASSIGNMENT HISTORY / CHAIN OF TITLE
The following assignment history is recorded with the United States Patent and Trademark Office for U.S. Patent No. 10,234,847 B2:
U.S. Patent No. 10,234,847 B2 was originally filed by and assigned to Optiwave Semiconductor Corp., Santa Clara, California. The patent remains assigned to Optiwave Semiconductor Corp. No change in assignment has occurred.
Relationship to the '562 Patent (U.S. Patent No. 9,678,562). The '847 Patent is a continuation-in-part of Application No. 14/551,230, which issued as U.S. Patent No. 9,678,562 on June 13, 2017. The '562 Patent was originally filed by and assigned to Solara Optics, Inc. Optiwave Semiconductor Corp. acquired the '562 Patent, along with eleven other patents and patent applications (the "Solara IP Portfolio"), from Solara Optics, Inc. pursuant to an Asset Purchase Agreement dated June 15, 2018. The aggregate purchase price for the Solara IP Portfolio was $34.5 million. The assignment of the '562 Patent from Solara Optics, Inc. to Optiwave Semiconductor Corp. was recorded with the USPTO on July 2, 2018 at Reel/Frame 046352/0118.
It is important to note that while the '562 Patent was acquired from Solara Optics, the '847 Patent was filed by Optiwave Semiconductor Corp. itself on September 14, 2016, prior to the acquisition of the Solara IP Portfolio. The '847 Patent claims the benefit of priority through the continuation chain to the provisional application (Application No. 62/086,471) filed December 2, 2013. The continuation-in-part relationship between the '847 Patent and the '562 Patent establishes that these patents are in the same patent family, with interrelated prosecution histories relevant to claim construction and validity analyses for both patents.
CERTIFICATION
UNITED STATES PATENT AND TRADEMARK OFFICE
OFFICE OF PATENT LEGAL ADMINISTRATION
I hereby certify that the attached is a true and correct copy of United States Patent No. 10,234,847 B2, entitled "Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss," issued March 19, 2019, to inventor(s) Jian-Wei Huang, Nikolai Petrov, and Emily R. Vasquez, assigned to Optiwave Semiconductor Corp., as it appears in the records of the United States Patent and Trademark Office.
This certified copy comprises the patent's front page, specification, claims, drawings, and all associated data as recorded in the official patent file.
This certification is provided under the authority of the Director of the United States Patent and Trademark Office, pursuant to 37 C.F.R. § 1.14 and the provisions of 35 U.S.C. § 10.
UNITED STATES PATENT AND TRADEMARK OFFICE
By: ________
Certifying Officer Office of Patent Legal Administration
Date of Certification: April 15, 2024
[SEAL OF THE UNITED STATES PATENT AND TRADEMARK OFFICE]
RELEVANCE OF EXHIBIT A TO THE PRESENT LITIGATION
The following summary is provided by counsel for Plaintiff Optiwave Semiconductor Corp. for the convenience of the Court and does not form part of the certified patent document reproduced above.
U.S. Patent No. 10,234,847 (the "'847 Patent") is one of the patents-in-suit in this action and is central to Plaintiff Optiwave Semiconductor Corp.'s ("OWS") claims of patent infringement against Defendant Lumicore Technologies, Inc. ("Lumicore"). The following summarizes the key litigation touchpoints relevant to this patent:
Infringement. OWS asserts that Lumicore's LumiLink 400G-ZR+ optical transceiver module (commercially launched in Q3 2022; FY 2023 revenue of approximately $94.8 million) and LumiLink 800G-DR8 optical transceiver module (commercially launched in Q1 2023; FY 2023 revenue of approximately $128.4 million) infringe Claims 1, 3, 5, 9, and 14 of the '847 Patent. OWS's infringement contentions are supported by independent third-party teardown analyses conducted by Benchmark Semiconductor Analysis, LLC. The Benchmark teardown report for the LumiLink 400G-ZR+, dated December 12, 2022, and the Benchmark teardown report for the LumiLink 800G-DR8, dated June 2023, each confirmed the presence of waveguide multiplexer structures in the accused products that correspond to the claimed elements of the asserted claims. Detailed infringement claim charts mapping each limitation of each asserted claim to specific structures identified in the Benchmark teardown reports were served on Lumicore on September 16, 2024.
Claim Construction. The term "waveguide multiplexer" as used in independent Claim 1 of the '847 Patent is one of the fourteen (14) disputed claim terms identified in the parties' Joint Claim Construction Statement, filed on October 28, 2024. OWS proposes that "waveguide multiplexer" should be construed to mean "an optical device that combines multiple optical signals of different wavelengths onto a single waveguide." Lumicore proposes the narrower construction "an arrayed waveguide grating that combines optical signals using a slab coupler and phase-shifted waveguide array." OWS submits that the '847 Patent specification's discussion of multiple multiplexer architectures — including AWGs, MZI-based multiplexers, star couplers, and MMI couplers — in both the background and detailed description sections supports OWS's broader construction and forecloses Lumicore's attempt to limit the claim scope to a single embodiment. The Markman hearing on claim construction is scheduled for March 14, 2025 before the Honorable Judge James R. Gilstrap.
Additionally, Claim 9 contains the term "means for coupling optical signals from the single output waveguide into a single-mode optical fiber," which may invoke 35 U.S.C. § 112(f) (means-plus-function). The corresponding structure disclosed in the specification includes a grating coupler and an edge coupler with a spot-size converter, and equivalents thereof.
Lumicore has further argued in its claim construction briefing that independent Claim 1 should be narrowly construed in light of the additional limitations recited in dependent Claims 3 and 5. OWS has countered that the doctrine of claim differentiation precludes reading the narrower limitations of dependent claims into the broader independent claim.
Invalidity. Lumicore's invalidity contentions, served on October 14, 2024, cite six (6) prior-art references against the asserted claims of the '847 Patent. Lumicore's primary anticipation reference under 35 U.S.C. § 102 is Takahashi et al., "Low-Loss Silicon Photonic Waveguide Multiplexer with Sub-Decibel Insertion Loss," IEEE Photonics Technology Letters, Vol. 26, No. 6, pp. 601–604 (March 15, 2014). Lumicore further relies on PCT/EP2015/071234 (Simonsen, published September 17, 2015) in combination with other references for obviousness under 35 U.S.C. § 103. OWS notes that both Takahashi and Simonsen were before the Examiner during prosecution of the '847 Patent and were cited in the "References Cited" section of the issued patent, and therefore carry a presumption of validity under 35 U.S.C. § 282 that Lumicore must overcome by clear and convincing evidence.
Patent Family. The '847 Patent is in the same patent family as U.S. Patent No. 9,678,562 (the "'562 Patent"), with a continuation-in-part relationship. The '562 Patent is also asserted in this litigation. The prosecution histories of the two patents are interrelated and relevant to claim construction and validity analyses for both patents. The shared priority chain and overlapping prosecution history may bear on the construction of common claim terms and on the scope of prior-art defenses asserted by Lumicore.
IPR Deadline. Lumicore has reserved its right to petition for inter partes review of the asserted claims of the '847 Patent. The one-year statutory deadline under 35 U.S.C. § 315(b) for filing an IPR petition is May 1, 2025.
CERTIFICATE OF SERVICE: I hereby certify that on April 22, 2024, a true and correct copy of the foregoing Exhibit A was served on all counsel of record via the Court's CM/ECF electronic filing system.
CALDERWOOD & HARKNESS LLP
By: ________
Alan Ngo (CA Bar No. 246718) Attorneys for Plaintiff Optiwave Semiconductor Corp.
Date: April 22, 2024
OPTIWAVE SEMICONDUCTOR CORP.,
<!-- indent:1 -->Plaintiff,<!-- /indent --> | Case No. 2:24-cv-00319-JRG
v. | JUDGE JAMES R. GILSTRAP
LUMICORE TECHNOLOGIES, INC.,
<!-- indent:1 -->Defendant.<!-- /indent --> | JURY TRIAL DEMANDED
(12) United States Patent | (10) Patent No.: US 10,234,847 B2
Huang et al. | (45) Date of Patent: March 19, 2019
Patent No. | Date | Inventor(s)
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Publication No. | Country | Date
EP 2 856 215 A1 | EP | April 8, 2015
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Reel/Frame | Date Recorded | Assignor | Assignee | Description
039812/0450 | September 14, 2016 | Jian-Wei Huang; Nikolai Petrov; Emily R. Vasquez | Optiwave Semiconductor Corp. | Assignment of Application No. 15/265,418 at filing

EXHIBIT A

UNITED STATES DISTRICT COURT FOR THE EASTERN DISTRICT OF TEXAS MARSHALL DIVISION

CERTIFIED COPY OF U.S. PATENT NO. 10,234,847

CALDERWOOD & HARKNESS LLP

WHITMORE & CALLAHAN LLP

UNITED STATES PATENT

US 10,234,847 B2

G02B 6/12 (2006.01) G02B 6/293 (2006.01) H04J 14/02 (2006.01)

U.S. PATENT DOCUMENTS

FOREIGN PATENT DOCUMENTS

OTHER PUBLICATIONS

DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS

SPECIFICATION

MULTI-CHANNEL SILICON PHOTONIC WAVEGUIDE MULTIPLEXER WITH LOW INSERTION LOSS

FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION

SUMMARY OF THE INVENTION

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

INDUSTRIAL APPLICABILITY

CERTIFICATE OF CORRECTION / REEXAMINATION HISTORY

ASSIGNMENT HISTORY / CHAIN OF TITLE

CERTIFICATION

UNITED STATES PATENT AND TRADEMARK OFFICE

OFFICE OF PATENT LEGAL ADMINISTRATION

UNITED STATES PATENT AND TRADEMARK OFFICE

RELEVANCE OF EXHIBIT A TO THE PRESENT LITIGATION

CALDERWOOD & HARKNESS LLP

OPTIWAVE SEMICONDUCTOR CORP.,

LUMICORE TECHNOLOGIES, INC.,

Record

Parties

Dates

Amounts