UNITED STATES PATENT AND TRADEMARK OFFICE
UTILITY PATENT APPLICATION (Non-Provisional under 35 U.S.C. § 111(a))
Application Serial Number: 17/814,057
Filing Date: July 21, 2023
Art Unit: To Be Assigned
Calderwood & Harkness LLP 555 California Street, 42nd Floor San Francisco, CA 94104
Attention: Christy Bauer (Reg. No. 74,329)
C&H Matter No. 1014-00005
FILING TRANSMITTAL
Application Type: Utility Patent Application (Non-Provisional) under 35 U.S.C. § 111(a)
Application Serial Number: 17/814,057
Filing Date: July 21, 2023
Art Unit: To be assigned by the United States Patent and Trademark Office
Applicant / Assignee: Optiwave Semiconductor Corp., a corporation organized and existing under the laws of the State of Delaware, having its principal place of business at 4710 Ridgeview Parkway, Suite 300, Santa Clara, CA 95054; Employer Identification Number (EIN): 83-2947105; Delaware Division of Corporations File No.: 7284931
Correspondence Address: Calderwood & Harkness LLP, 555 California Street, 42nd Floor, San Francisco, CA 94104; Attention: Christy Bauer (USPTO Registration No. 74,329); Telephone: (415) 555-8200; Facsimile: (415) 555-8201
Customer Number / Filing Reference: C&H Matter No. 1014-00005
Entity Status: Small Entity (certified under 37 C.F.R. § 1.27)
Filed via: USPTO Electronic Filing System (EFS-Web)
Prepared by: Christy Bauer, Esq. (USPTO Reg. No. 74,329) and Peter Vassiliev, Ph.D. (USPTO Reg. No. 79,514), Calderwood & Harkness LLP
Responsible Partner: Catherine Bloom, Esq. (USPTO Reg. No. 58,412), Calderwood & Harkness LLP
The following documents are submitted herewith in connection with the above-identified utility patent application:
1. Specification (including Title, Cross-Reference to Related Applications, Statement Regarding Federally Sponsored Research, Field of the Invention, Background of the Invention, Brief Summary of the Invention, Brief Description of the Drawings, and Detailed Description of the Invention)
2. Claims (25 claims: 3 independent, 22 dependent)
3. Abstract of the Disclosure
4. Drawings (FIGS. 1–9)
5. Application Data Sheet (ADS)
6. Combined Inventor Declaration under 37 C.F.R. § 1.63
7. Assignment (Nunc Pro Tunc)
8. Information Disclosure Statement (IDS) with attached references
9. Power of Attorney
10. Fee Transmittal with payment authorization
APPLICATION DATA SHEET (ADS) — KEY FIELDS
Applicant Information.
Inventor Information.
Domestic Benefit / Priority Data
This application claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. Provisional Application No. 63/297,841, entitled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture," filed on January 10, 2022 (expired January 10, 2023). The provisional application was originally filed by prior counsel Kessler & Morin LLP on behalf of Optiwave Semiconductor Corp. Prosecution was transitioned to Calderwood & Harkness LLP upon engagement opened February 14, 2022.
Related Applications in the Family:
Foreign Priority Data
None claimed directly. Priority flows through U.S. Provisional Application No. 63/297,841.
Assignee Information.
Assignment was executed contemporaneously with the filing of this application and has been submitted for recording at the USPTO Assignment Recordation Branch.
SPECIFICATION
TITLE OF THE INVENTION
Method of Fabricating Segmented Traveling-Wave Electrodes for Silicon-Photonic Mach-Zehnder Modulators
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 63/297,841, filed January 10, 2022, and entitled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture," the entire disclosure of which is incorporated herein by reference in its entirety for all purposes.
This application is related to the following co-pending patent applications, each of which is also incorporated herein by reference in its entirety:
U.S. Patent Application No. 17/672,204, filed January 9, 2023, entitled "Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture Having Tapered Impedance-Matching Transitions," which is directed to the modulator device architecture;
U.S. Patent Application No. 17/672,311, filed March 15, 2023, which is a continuation of U.S. Application No. 17/672,204;
U.S. Patent Application No. 17/672,489, filed June 22, 2023, which is a continuation-in-part of U.S. Application No. 17/672,204;
International Patent Application No. PCT/US2023/010584, filed January 9, 2023, under the Patent Cooperation Treaty; and
International Patent Application No. PCT/US2023/010612, filed January 9, 2023, under the Patent Cooperation Treaty.
All of the above-identified related applications share common inventors, namely Dr. Rajan Menon, Dr. Lena Strickland, Dr. Feng-Yi Chen, and Dr. Arjun Dasgupta, and are assigned to Optiwave Semiconductor Corp. of Santa Clara, California.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable. The invention described herein was not made with government support, and no federal agency has rights in this invention.
FIELD OF THE INVENTION
The present invention relates generally to methods of fabricating electrodes for high-speed electro-optic modulators. More particularly, the invention relates to a multi-step lithographic and metallization process for fabricating segmented traveling-wave electrodes with tapered impedance-matching sections for use in silicon-photonic Mach-Zehnder modulator (MZM) structures designed for 800G and 1.6T data-center optical transceiver applications. The invention is applicable to the fields of silicon photonics, photonic integrated circuits (PICs), Mach-Zehnder modulators, traveling-wave electrode design and fabrication, impedance matching in radio-frequency (RF) electrode structures, data-center interconnects, and high-speed optical modulation systems.
BACKGROUND OF THE INVENTION
1. General Background
The explosive growth of cloud computing, artificial intelligence (AI) workloads, machine learning training clusters, and hyperscale data-center infrastructure has driven an insatiable demand for higher-bandwidth optical interconnects. Modern data centers require optical transceiver modules operating at aggregate data rates of 800 Gbps (800G) and, increasingly, 1.6 Tbps (1.6T) per port to support spine-leaf switching architectures, disaggregated computing, and high-radix switch ASICs with ever-increasing I/O bandwidth requirements. These data rates necessitate electro-optic modulator components capable of operating at symbol rates of 100 GBaud and beyond, utilizing advanced modulation formats such as PAM4 (4-level pulse-amplitude modulation) for intensity-modulated direct-detect (IM-DD) links and 16-QAM or 64-QAM for coherent optical links.
Silicon-photonic Mach-Zehnder modulators (MZMs) have emerged as key enablers of next-generation coherent and intensity-modulated optical transceivers. Silicon photonics technology leverages mature complementary metal-oxide-semiconductor (CMOS) fabrication infrastructure to produce photonic integrated circuits (PICs) at wafer scale with high yield and low cost. The silicon-photonic MZM operates by modulating the refractive index of a silicon waveguide through the free-carrier plasma dispersion effect, typically implemented via a reverse-biased PN junction or a PIN junction formed within the waveguide core. An RF modulating signal applied to an electrode structure along the waveguide induces a phase shift in the propagating optical mode, and the Mach-Zehnder interferometer converts this phase modulation into intensity modulation at the output.
The traveling-wave electrode (TWE) design has become the state-of-the-art approach for achieving broadband electro-optic modulation bandwidth in silicon-photonic MZMs. In a traveling-wave configuration, the RF modulating signal co-propagates with the optical mode along the length of the phase-shifter waveguide, such that the modulating voltage continuously interacts with the optical field over the entire electrode length. This distributed interaction eliminates the RC bandwidth limitation inherent in lumped-element electrode designs and, in principle, enables modulation bandwidths limited only by velocity mismatch between the RF and optical signals, RF propagation loss, and impedance matching at the electrode termination.
To optimize the performance of traveling-wave electrode structures, segmented electrode architectures have been developed. In a segmented TWE design, the electrode is divided into a plurality of discrete segments, each of which may have independently optimized geometry (width, thickness, and spacing) to achieve a desired characteristic impedance and RF propagation velocity. Segmentation allows the designer to tailor the velocity-matching condition along the electrode length, compensate for the inherent velocity mismatch between the microwave signal (which propagates at a velocity determined by the effective dielectric constant of the electrode transmission line) and the optical mode (which propagates at a velocity determined by the effective refractive index of the silicon waveguide), and optimize the bandwidth-voltage product of the modulator. Segmented TWE architectures have been shown to improve modulation efficiency, extend bandwidth, and enable operation at the data rates required for 800G and 1.6T transceiver applications.
2. Prior Art Limitations
Despite the advantages of segmented traveling-wave electrode architectures, existing fabrication processes for segmented TWEs suffer from significant limitations that constrain modulator performance. A principal limitation is the occurrence of impedance discontinuities at the junctions between adjacent electrode segments. In conventional fabrication processes, each electrode segment is defined as a discrete metal structure with an abrupt termination at each end. At the boundary between two segments, the abrupt change in electrode geometry (and, consequently, in characteristic impedance) creates a discontinuity in the microwave transmission line. These impedance discontinuities cause signal reflections at each segment boundary, which reduce the effective modulation bandwidth, introduce ripple in the electro-optic frequency response, and degrade the overall modulation performance of the device.
The severity of the impedance discontinuity problem is compounded in segmented electrode designs that intentionally vary the characteristic impedance from segment to segment for velocity-matching optimization. In such designs, adjacent segments may have significantly different impedances (e.g., differing by 5–15 Ω), and the abrupt transitions between these impedance values generate correspondingly large reflection coefficients. The cumulative effect of multiple reflections from multiple segment boundaries can severely limit the usable bandwidth of the modulator, particularly at the high frequencies required for 100+ GBaud operation.
Additional challenges in the prior art relate to uniform electrode thickness control, segment alignment accuracy, and integration with the underlying silicon-photonic waveguide layers. Conventional single-step metallization processes, in which all electrode segments are defined and deposited in a single lithographic and deposition step, do not adequately address the need for graded or tapered impedance transitions between electrode segments. While some prior art approaches have attempted to address impedance matching by modifying electrode geometry at segment boundaries (e.g., by varying electrode width), these approaches are limited in their effectiveness and introduce additional design constraints that may compromise other performance parameters such as RF loss and velocity matching.
The prior art includes, among other references, U.S. Patent No. 10,823,417 and U.S. Patent No. 11,105,662, both assigned to Pinnacle Optics, Inc., which disclose segmented traveling-wave electrode geometries for silicon-photonic modulators. However, these references do not teach or suggest tapered impedance-matching transitions between electrode segments, and the electrode structures disclosed therein are characterized by abrupt segment junctions that give rise to the impedance discontinuity problems described above.
3. Objects of the Invention
In view of the foregoing, it is an object of the present invention to provide an improved method of fabricating segmented traveling-wave electrodes with precisely controlled tapered impedance-matching transitions between adjacent electrode segments.
It is a further object of the present invention to enable high-yield, wafer-scale manufacturing of tapered-segment traveling-wave electrodes integrated with silicon-photonic Mach-Zehnder modulator waveguide structures using processes that are compatible with standard semiconductor fabrication facilities.
It is yet a further object of the present invention to reduce impedance mismatch and microwave signal reflections at electrode segment boundaries, thereby improving the electro-optic modulation bandwidth and frequency response flatness of silicon-photonic MZMs.
It is still a further object of the present invention to achieve fabrication tolerances and electrode performance characteristics compatible with 800G and 1.6T modulation performance requirements, including 3-dB electro-optic bandwidths exceeding 50 GHz and preferably exceeding 60 GHz.
Other objects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a multi-step lithographic and metallization process for fabricating segmented traveling-wave electrodes on a silicon-photonic substrate, wherein at least one electrode segment includes a tapered impedance-matching region formed through a graded-thickness deposition technique. The method overcomes the limitations of the prior art by providing a smooth, continuously-graded impedance transition between adjacent electrode segments, thereby eliminating the abrupt impedance discontinuities that cause microwave reflections and limit modulation bandwidth in conventional segmented traveling-wave electrode structures.
In a first aspect of the invention, the method comprises the following principal steps:
(1) Forming a silicon-photonic waveguide layer on a silicon-on-insulator (SOI) substrate, including PN junction or PIN junction phase-shifter regions within at least one arm of a Mach-Zehnder interferometer waveguide structure;
(2) Depositing a dielectric interlayer over the waveguide structure and forming contact vias through the dielectric to the doped silicon contact regions of the phase-shifter;
(3) Depositing a first metal layer to define primary electrode segments using a first lithographic mask, the electrode segments being patterned as discrete metal structures separated by gaps at intended transition zones;
(4) Applying a second lithographic mask having a graded opening profile over the gap regions between adjacent electrode segments, the graded opening profile being configured to produce a spatially varying deposition aperture;
(5) Depositing a second metal layer through the graded openings to form tapered thickness profiles in the transition regions, creating smooth impedance transitions between adjacent electrode segments; and
(6) Optionally, performing a planarization step and depositing a capping metal layer over the entire electrode structure for reduced resistivity and improved RF performance, followed by passivation.
The graded opening profile of the second lithographic mask may be implemented using a gray-scale mask, a mask comprising sub-resolution apertures of spatially varying density or size, or a tilted or stepped exposure technique, each of which produces a photoresist opening with a spatially varying dimension that controls the local thickness of the deposited second metal layer.
The resulting tapered impedance-matching regions provide impedance continuity across segment boundaries, reducing microwave signal reflection coefficients from approximately 0.15 (typical of conventional abrupt-junction designs) to less than 0.02 at each transition, and enabling extended electro-optic bandwidths exceeding 60 GHz. The fabrication process is compatible with standard CMOS back-end-of-line (BEOL) processing, facilitating integration into existing silicon-photonic foundry workflows for high-volume manufacturing.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a cross-sectional view of a silicon-photonic Mach-Zehnder modulator device showing the silicon-on-insulator (SOI) substrate, the waveguide layer, the PN junction phase-shifter, and the segmented traveling-wave electrode structure with tapered impedance-matching regions, constructed in accordance with an embodiment of the present invention.
FIG. 2 is a top-down schematic view of the segmented traveling-wave electrode layout showing multiple electrode segments, tapered transition zones between adjacent segments, and signal and ground electrode traces, in accordance with an embodiment of the present invention.
FIG. 3A is a cross-sectional view illustrating the SOI substrate with the silicon-photonic waveguide and PN junction phase-shifter formed therein, at an initial stage of the fabrication process according to an embodiment of the present invention.
FIG. 3B is a cross-sectional view illustrating the first dielectric interlayer deposition and via formation to waveguide contact regions, at a subsequent stage of the fabrication process.
FIG. 3C is a cross-sectional view illustrating the first metal layer deposition and patterning to form primary electrode segments using a first lithographic mask, at a subsequent stage of the fabrication process.
FIG. 3D is a cross-sectional view illustrating the application of a second lithographic mask with a graded opening profile over transition regions between adjacent electrode segments.
FIG. 3E is a cross-sectional view illustrating the second metal layer deposition through the graded openings to form a tapered thickness profile in the transition region between adjacent electrode segments.
FIG. 3F is a cross-sectional view illustrating the completed electrode structure following planarization, capping metal deposition, and passivation.
FIG. 4 is a detail view of the graded lithographic mask opening profile, showing the relationship between mask aperture width variation and the resulting metal thickness gradient in the transition region.
FIG. 5 is a graph plotting characteristic impedance (Z₀) as a function of position along the electrode length, comparing a conventional abrupt-junction segmented electrode (dashed line) versus the tapered-transition electrode fabricated by the method of the present invention (solid line).
FIG. 6 is a graph plotting electro-optic frequency response (S21, in dB) as a function of modulation frequency for modulators fabricated with the inventive process (solid line) versus a conventional process (dashed line), demonstrating the extended 3-dB electro-optic bandwidth achieved by the present invention.
FIG. 7 is a flowchart illustrating the overall fabrication method of the present invention.
FIG. 8 is a top-down scanning electron micrograph (SEM) of a prototype tapered impedance-matching transition region fabricated according to an embodiment of the present invention.
FIG. 9 is a cross-sectional transmission electron micrograph (TEM) image of the graded metal thickness profile at a tapered transition region, fabricated according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Throughout the drawings, like numerals refer to like elements. The following description sets forth numerous specific details in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well-known process operations and structures have not been described in detail so as not to obscure the present invention.
Overview of the Silicon-Photonic MZM Architecture
Referring first to FIG. 1, there is shown a cross-sectional view of a silicon-photonic Mach-Zehnder modulator (MZM) device 100 constructed in accordance with an embodiment of the present invention. The device 100 is fabricated on a silicon-on-insulator (SOI) platform and includes an SOI substrate 102 comprising a silicon handle wafer 104, a buried oxide (Box) layer 106, and a silicon device layer 108. The box layer 106 serves as a lower cladding for the optical waveguide and provides optical confinement of the guided mode.
The silicon device layer 108 is patterned to form silicon rib waveguides 110 that define the two arms of the Mach-Zehnder interferometer. Each waveguide arm includes a PN junction phase-shifter region 112, which is formed by ion implantation of p-type and n-type dopants into opposite lateral halves of the waveguide rib. When a reverse-bias voltage is applied across the PN junction 112, the free-carrier concentration in the junction depletion region changes, which in turn modulates the refractive index of the silicon waveguide through the free-carrier plasma dispersion effect. This refractive index modulation produces a phase shift in the optical mode propagating through the waveguide arm, and the Mach-Zehnder interferometer converts the differential phase shift between the two arms into an intensity modulation at the output optical port.
A dielectric interlayer 114, typically comprising silicon dioxide (SiO₂), is deposited over the waveguide structure and planarized by chemical-mechanical planarization (CMP). Contact vias 116 extend through the dielectric interlayer 114 to the heavily-doped p+ and n+ contact regions 118, 120 on either side of the PN junction 112, providing electrical connectivity between the electrode structure and the phase-shifter.
A segmented traveling-wave electrode structure 130 is formed over the dielectric interlayer 114. The electrode structure 130 comprises a signal electrode 132 and ground electrodes 134 arranged in a coplanar waveguide (CPW) or ground-signal-ground (GSG) configuration. The signal electrode 132 is electrically connected to the p-type (or n-type) contact region through the contact vias 116, and the ground electrodes 134 are electrically connected to the n-type (or p-type) contact regions through corresponding contact vias.
The signal electrode 132 is segmented into a plurality of discrete electrode segments 132a, 132b, 132c, etc., along the propagation direction of the optical waveguide. Between adjacent electrode segments, tapered impedance-matching regions 136 provide a smooth, continuous transition in the characteristic impedance of the electrode transmission line. These tapered impedance-matching regions 136 are a key feature of the present invention, and their fabrication is described in detail below.
The role of the traveling-wave electrode structure 130 is to apply a modulating RF signal along the length of the PN junction phase-shifter 112 such that the RF signal co-propagates with the optical mode in the waveguide. In a well-designed traveling-wave electrode, the velocity of the RF signal on the electrode transmission line is matched to the group velocity of the optical mode in the silicon waveguide, and the characteristic impedance of the electrode is matched to the source and termination impedances (typically 50 Ω) to minimize reflections at the input and output ports.
Segmentation of the electrode into discrete segments provides additional design flexibility for optimizing the velocity-matching condition. Each segment may have independently optimized geometry — including electrode width, thickness, and gap to the ground electrodes — to achieve a desired local characteristic impedance and local RF propagation velocity. By varying the segment geometry along the electrode length, the designer can compensate for the inherent velocity mismatch between the microwave signal and the optical mode, and can optimize the cumulative electro-optic phase shift for maximum modulation efficiency.
However, in conventional segmented traveling-wave electrode designs, the transitions between adjacent segments are abrupt. Each segment terminates with a sharp edge, and the adjacent segment begins with a correspondingly sharp edge, creating a discrete impedance discontinuity at each segment boundary. These impedance discontinuities act as partial reflectors for the propagating microwave signal, causing a portion of the RF energy to be reflected back toward the source. The reflected signals interfere with the forward-propagating signal, creating standing waves, ripple in the frequency response, and an effective reduction in the usable modulation bandwidth. The cumulative effect of multiple segment-boundary reflections along the electrode length can be severe, particularly in designs having many segments (e.g., 6–12 segments) with intentionally varying impedance values.
The present invention addresses this fundamental limitation by providing a fabrication process that creates tapered impedance-matching regions 136 between adjacent electrode segments, such that the characteristic impedance varies continuously and smoothly through the transition zone rather than changing abruptly. As will be described in detail below, the tapered regions are formed using a second lithographic step with a graded opening profile that controls the local metal thickness in the transition zone, thereby controlling the local characteristic impedance.
Substrate Preparation (Referring to FIG. 3A)
Referring now to FIG. 3A, the fabrication process begins with an SOI substrate 102 comprising a silicon handle wafer 104 having a thickness of approximately 700–750 µm, a buried oxide (Box) layer 106 having a thickness of approximately 2–3 µm (preferably about 2 µm), and a silicon device layer 108 having a thickness of between 200 nm and 300 nm (preferably about 220 nm). The SOI substrate 102 may be obtained from a commercial supplier and is of the type commonly used in silicon-photonic foundry processes.
Silicon rib waveguides 110 for the MZM arms are formed in the silicon device layer 108 by lithographic patterning and etching. In a preferred embodiment, the rib waveguides 110 are defined by a partial etch of the silicon device layer 108, leaving a slab region 111 on either side of the rib. The rib width is preferably between 400 nm and 600 nm (more preferably about 500 nm), and the slab height is preferably between 70 nm and 110 nm (more preferably about 90 nm), with the rib height (measured from the top of the slab to the top of the rib) being the balance of the device layer thickness (e.g., approximately 130 nm for a 220 nm device layer with a 90 nm slab). These dimensions are selected to support single-mode propagation at the operating wavelength (typically 1310 nm for data-center applications or 1550 nm for telecommunications applications) while providing adequate overlap between the optical mode and the PN junction depletion region for efficient electro-optic modulation.
PN junction phase-shifter regions 112 are formed within the waveguide arms by ion implantation. In a preferred embodiment, a lateral PN junction is formed by implanting p-type dopants (e.g., boron) into one lateral half of the waveguide rib and n-type dopants (e.g., phosphorus) into the other lateral half. The junction is positioned approximately at the center of the waveguide rib to maximize the overlap between the optical mode and the carrier-depletion region.
The doping process typically involves multiple implantation steps at different energies and doses to achieve the desired doping profile. In a preferred embodiment, the p-type doping concentration in the active junction region is between about 3 × 10¹⁷ cm⁻³ and about 1 × 10¹⁸ cm⁻³, and the n-type doping concentration is between about 3 × 10¹⁷ cm⁻³ and about 1 × 10¹⁸ cm⁻³. Highly-doped p+ and n+ contact regions 118, 120 are formed at a lateral offset from the waveguide rib (typically 500–1000 nm from the rib edge) by a separate implantation step at higher dose, with doping concentrations of about 1 × 10²⁰ cm⁻³ or greater, to provide low-resistance ohmic contacts to the electrode structure. The junction depth is typically the full thickness of the silicon device layer (i.e., about 220 nm).
Following ion implantation, a thermal anneal is performed to activate the dopants and repair implantation damage. The anneal is typically a rapid thermal anneal (RTA) at a temperature of approximately 1000–1050°C for a duration of approximately 5–10 seconds. The anneal conditions are selected to achieve adequate dopant activation while minimizing dopant diffusion, which could broaden the junction profile and degrade modulation efficiency.
In an alternative embodiment, a PIN junction phase-shifter may be used instead of a PN junction. In the PIN embodiment, an intrinsic (undoped) silicon region is interposed between the p-type and n-type regions within the waveguide rib. The PIN junction configuration can provide higher modulation efficiency (i.e., greater phase shift per unit voltage) at the cost of somewhat higher RF loss, and may be preferred in certain applications.
Dielectric Interlayer and Via Formation (Referring to FIG. 3B)
Referring now to FIG. 3B, following formation of the PN junction phase-shifter regions 112 and the associated contact regions 118, 120, a dielectric interlayer 114 is deposited over the entire waveguide and phase-shifter structure. The dielectric interlayer 114 preferably comprises silicon dioxide (SiO₂), deposited by plasma-enhanced chemical vapor deposition (PECVD) to a thickness of approximately 2–4 µm. Other suitable dielectric materials include low-k dielectrics such as fluorinated silicon dioxide (FSG) or organosilicate glass (OSG), which may provide reduced RF loss in the electrode transmission line at the cost of somewhat reduced mechanical robustness.
The deposited dielectric interlayer 114 is planarized by chemical-mechanical planarization (CMP) to achieve a surface flatness suitable for the subsequent metallization steps. The post-CMP surface roughness is preferably less than 2 nm RMS, and the thickness uniformity across the wafer is preferably within ±5% of the target thickness. The final thickness of the planarized dielectric interlayer 114 above the top of the waveguide rib is preferably between about 1.5 µm and about 3.0 µm, and is selected to provide adequate electrical isolation between the electrode structure and the silicon waveguide while minimizing the distance between the electrode and the PN junction depletion region (which affects modulation efficiency).
Contact vias 116 are then formed through the dielectric interlayer 114 to provide electrical connection between the electrode structure and the heavily-doped p+ and n+ contact regions 118, 120 of the phase-shifter. The via formation process comprises lithographic patterning of a via mask on the dielectric surface, followed by anisotropic dry etching (e.g., reactive ion etching (RIE) using a fluorine-based chemistry) to create via openings extending through the full thickness of the dielectric interlayer 114 to expose the underlying silicon contact regions.
The via openings are then filled with a refractory metal plug material, preferably tungsten (W), deposited by chemical vapor deposition (CVD). Prior to tungsten deposition, a thin adhesion/barrier layer of titanium (Ti) and titanium nitride (TiN) is deposited by physical vapor deposition (PVD) to promote adhesion and prevent tungsten diffusion into the dielectric. The tungsten CVD process fills the via openings conformally, and excess tungsten on the dielectric surface is removed by a second CMP step, which planarizes the tungsten via plugs 116 flush with the top surface of the dielectric interlayer 114. The resulting structure presents a planar surface with exposed tungsten via plug tops, ready for metallization.
First Metal Layer — Primary Electrode Segment Formation (Referring to FIG. 3C)
Referring now to FIG. 3C, a first metal layer 140 is deposited over the planarized dielectric surface. The first metal layer 140 may comprise aluminum (Al), copper (Cu), or gold (Au), depending on the specific process flow and performance requirements. In a preferred embodiment, the first metal layer 140 comprises aluminum deposited by physical vapor deposition (PVD/sputtering) to a thickness of between about 1.5 µm and about 3.0 µm. In an alternative preferred embodiment, the first metal layer 140 comprises copper deposited by an electroplating process over a PVD seed layer, which provides lower resistivity and reduced RF loss at the cost of additional process complexity (including the need for a barrier layer to prevent copper diffusion).
A first lithographic mask 142 is applied over the first metal layer 140. The first lithographic mask 142 defines the primary electrode segment geometries, including the signal electrode segments 132a, 132b, 132c, etc., the ground electrode traces 134, and RF input and output pads 138. The mask pattern is transferred to the first metal layer 140 by etching — either wet etching (e.g., using a phosphoric/acetic/nitric acid mixture for aluminum) or dry etching (e.g., reactive ion etching (RIE) using a chlorine-based chemistry for aluminum, or a fluorine-based chemistry for copper).
The etching step defines discrete electrode segments 132a, 132b, 132c, etc., with gaps 144 at the intended transition zones between adjacent segments. Each electrode segment has a length, measured along the direction of RF propagation (which is also the direction of optical propagation in the waveguide), of between about 200 µm and about 2 mm, and preferably between about 300 µm and about 1 mm. The total number of electrode segments is typically between 3 and 12, depending on the total electrode length and the optimization requirements for velocity matching and impedance control.
The width of each electrode segment, measured perpendicular to the direction of RF propagation, is selected to achieve a target characteristic impedance for that segment. In a preferred embodiment, the signal electrode width is between about 5 µm and about 30 µm, and the gap between the signal electrode and each ground electrode is between about 5 µm and about 50 µm. The target characteristic impedance for each segment is between about 25 Ω and about 75 Ω, and preferably between about 35 Ω and about 65 Ω. In some embodiments, adjacent segments are designed with intentionally different characteristic impedances (e.g., segment 132a at 45 Ω and segment 132b at 52 Ω) to optimize the velocity-matching condition.
The gaps 144 between adjacent electrode segments have a length (measured along the direction of RF propagation) of between about 20 µm and about 120 µm. It is in these gap regions that the tapered impedance-matching regions will be formed in the subsequent fabrication steps.
After patterning, the first lithographic mask (photoresist) is stripped, and the structure is cleaned to prepare for the second lithographic step.
Second Lithographic Mask — Graded Opening Profile (Referring to FIGS. 3D, 4)
Referring now to FIGS. 3D and 4, a photoresist layer 150 is applied over the patterned first metal layer 140, covering the electrode segments 132a, 132b, 132c, etc., the gaps 144, and the surrounding dielectric surface. The photoresist layer 150 is preferably a positive photoresist having a thickness of between about 2 µm and about 5 µm, sufficient to serve as a deposition mask for the subsequent metal deposition step.
The photoresist layer 150 is exposed using a second lithographic mask 152 that has a graded opening profile 154 at the transition regions corresponding to the gaps 144 between adjacent electrode segments. The graded opening profile 154 is a key feature of the present invention and is designed to produce a spatially varying exposure dose in the photoresist, resulting, after development, in a photoresist opening with a gradually varying aperture dimension.
In a first preferred embodiment, the graded opening profile 154 is implemented as a pattern of sub-resolution apertures 156 having a spatially varying density or size. The sub-resolution apertures 156 are features on the lithographic mask that are smaller than the resolution limit of the projection lithography system, such that individual apertures are not resolved in the photoresist but instead produce an effective exposure dose that depends on the local aperture density or total open-area fraction. By varying the density or size of the sub-resolution apertures 156 across the transition region, the effective exposure dose is smoothly varied, producing a photoresist opening with a gradually varying width (in the direction perpendicular to the transition region length) or a gradually varying depth.
In a second preferred embodiment, the graded opening profile 154 is formed using a gray-scale lithographic mask. A gray-scale mask has regions of continuously varying optical transmission, which produce a continuously varying exposure dose in the photoresist. After development, the photoresist thickness varies continuously across the gray-scale exposed region, creating a three-dimensional resist profile that serves as a deposition mask with a spatially varying effective aperture.
In a third preferred embodiment, the graded opening profile 154 is created by a tilted or stepped exposure technique, in which the substrate is tilted at a small angle relative to the exposure beam during a portion of the exposure, or multiple exposure steps at slightly different focal planes are used to create a graded resist profile.
Regardless of the specific implementation, the graded opening profile 154 is designed so that subsequent metal deposition through the developed photoresist opening produces a metal thickness that tapers smoothly from the full thickness of the primary electrode segment at one end of the transition region to a reduced thickness at the center of the gap, and then increases back to the full thickness of the adjacent primary electrode segment at the other end of the transition region. In alternative embodiments, the taper may be asymmetric, with the metal thickness tapering from the full thickness of a first segment to a different full thickness of a second segment.
Referring now to FIG. 4, the relationship between the mask aperture geometry and the resulting metal thickness gradient is illustrated in detail. In the exemplary embodiment shown, the graded opening profile 154 produces a photoresist opening whose effective width W(x) varies as a function of position x along the transition region (where x = 0 at the edge of the first segment and x = Ltaper at the edge of the second segment). The effective width W(x) increases from zero (or near-zero) at x = 0 to a maximum value Wmax at the center of the transition region (x = Ltaper/2), and then decreases back to zero (or near-zero) at x = Ltaper. In embodiments where the taper connects two segments of different impedance, the profile may be shifted or asymmetric.
The taper length L_taper is a critical design parameter and is preferably between about 20 µm and about 100 µm, and more preferably between about 30 µm and about 70 µm. The taper length is selected to be long enough to provide a sufficiently gradual impedance transition (which reduces reflections) but short enough to avoid excessive addition to the total electrode length (which could affect velocity matching and increase RF loss). Electromagnetic simulations, described further below, are used to optimize the taper length for a given modulator design.
Second Metal Layer Deposition — Tapered Impedance-Matching Region (Referring to FIG. 3E)
Referring now to FIG. 3E, following development and patterning of the photoresist layer 150 with the graded opening profile 154, a second metal layer 160 is deposited over the structure. The second metal layer 160 is preferably the same metal as the first metal layer 140 (e.g., aluminum, copper, or gold) to ensure metallurgical compatibility and to avoid the formation of galvanic interfaces that could cause corrosion or reliability issues.
The second metal layer 160 is deposited by a suitable deposition method, which may include physical vapor deposition (PVD/sputtering), electron-beam evaporation, or electroplating. PVD sputtering and electron-beam evaporation are preferred because they are directional deposition processes in which the deposited metal arrives at the substrate surface predominantly from a single direction (i.e., normal to the substrate surface). This directionality means that the amount of metal deposited at any given point on the substrate depends on the effective aperture of the photoresist opening above that point — regions beneath wider photoresist openings receive more metal than regions beneath narrower openings. Thus, the graded opening profile 154 of the photoresist layer 150 is faithfully transferred into a graded thickness profile of the deposited second metal layer 160.
In the transition region, the deposited second metal layer 160 has a tapered thickness profile 162 that varies continuously from a first thickness t₁ proximate the first electrode segment 132a to a second thickness t₂ at the center of the transition region, and then from t₂ to a third thickness t₃ proximate the second electrode segment 132b. In a symmetric taper between segments of equal impedance, t₁ = t₃ and t₂ is less than t₁. The tapered metal region physically and electrically bridges the gap 144 between the adjacent primary electrode segments 132a, 132b, creating a continuous metallic connection with a smoothly varying cross-section.
The characteristic impedance Z₀ of the electrode at any point along the taper is a function of the local metal cross-section (which depends on the local metal width and thickness), the properties of the underlying dielectric (including its thickness and dielectric constant), and the spacing to the ground electrodes 134. Because the metal thickness varies continuously through the taper region, the characteristic impedance also varies continuously, providing a smooth impedance transition from the characteristic impedance of segment 132a to the characteristic impedance of segment 132b. This continuous impedance transition eliminates the abrupt impedance discontinuity that exists in conventional segmented electrode designs, and dramatically reduces microwave signal reflections at the segment boundary.
In a preferred embodiment, the taper profile is designed so that the characteristic impedance varies according to a monotonic function of position along the taper. Several specific taper profile functions may be employed, including:
(i) A linear taper, in which the metal thickness (and corresponding impedance) varies linearly with position along the taper length;
(ii) A quadratic taper, in which the metal thickness varies as a second-order polynomial function of position;
(iii) An exponential taper, in which the impedance varies exponentially with position, providing a constant fractional impedance change per unit length; and
(iv) A Klopfenstein taper, which is an optimized taper profile derived from Chebyshev polynomial theory that provides the minimum taper length for a specified maximum passband reflection coefficient. The Klopfenstein taper is theoretically optimal in the sense that it minimizes the reflection coefficient over a specified bandwidth for a given taper length, and it is the preferred taper profile for applications requiring the highest bandwidth performance.
The specific taper profile function is implemented by designing the graded opening profile 154 of the second lithographic mask 152 to produce the corresponding metal thickness variation. The relationship between the mask aperture geometry and the metal thickness profile is determined by electromagnetic simulation and calibration experiments, and the mask design is adjusted accordingly.
Following deposition of the second metal layer 160, the photoresist layer 150 is stripped using a suitable solvent (e.g., acetone, N-methyl-2-pyrrolidone (NMP), or a commercially available photoresist stripper), leaving the patterned second metal layer 160 in the transition regions.
Planarization, Capping, and Passivation (Referring to FIG. 3F)
Referring now to FIG. 3F, following photoresist stripping, an optional planarization step is performed. In embodiments where the surface topography introduced by the two-step metallization process is significant, CMP or a controlled etch-back process may be used to partially planarize the electrode surface. The planarization step reduces surface roughness and step heights, which can affect the uniformity of subsequent deposited layers and the quality of RF probe or wire-bond contacts.
A thin capping metal layer 170 is then deposited over the entire electrode structure, including the primary electrode segments 132a, 132b, 132c, etc., and the tapered impedance-matching regions 136. The capping metal layer 170 preferably comprises gold (Au) or copper (Cu) having a thickness of between about 100 nm and about 500 nm. The capping metal layer 170 serves multiple functions: it reduces the overall sheet resistance of the electrode (improving RF performance by reducing ohmic loss), it provides a chemically stable surface for subsequent processing and for RF probe contact, and it encapsulates the underlying metal layers to prevent oxidation and corrosion.
Following deposition of the capping metal layer 170, a passivation dielectric layer 172 is deposited over the completed electrode structure. The passivation layer 172 preferably comprises silicon nitride (Si₃N₄) deposited by PECVD to a thickness of between about 200 nm and about 1 µm. The passivation layer 172 provides environmental protection for the electrode structure and prevents contamination during subsequent packaging and assembly operations.
Bond-pad windows 174 are opened in the passivation layer 172 at the locations of the RF input pad, RF output pad (or termination), and DC bias pads, by lithographic patterning and dry etching. The bond-pad windows 174 expose the underlying capping metal layer 170, allowing for RF probe access during on-wafer testing or for wire-bond/flip-chip assembly during packaging.
The completed structure is shown in cross-section in FIG. 3F and includes all of the layers described above: the SOI substrate 102, the PN junction phase-shifter waveguide 110/112, the dielectric interlayer 114, the contact vias 116, the primary electrode segments 132a, 132b (first metal layer 140), the tapered impedance-matching regions 136 (second metal layer 160), the capping metal layer 170, and the passivation layer 172.
Impedance Matching Performance (Referring to FIG. 5)
FIG. 5 is a graph illustrating the characteristic impedance Z₀ as a function of position along the electrode length for two structures: a conventional abrupt-junction segmented electrode (dashed line) and a tapered-transition electrode fabricated by the method of the present invention (solid line).
In the conventional structure, the impedance profile exhibits sharp discontinuities (step changes) at each segment boundary. For example, if segment 132a has a characteristic impedance of 45 Ω and segment 132b has a characteristic impedance of 52 Ω, the impedance in the conventional structure changes abruptly from 45 Ω to 52 Ω at the segment boundary. This abrupt impedance change produces a reflection coefficient Γ at the boundary given by:
Γ = (Z₂ − Z₁) / (Z₂ + Z₁)
For the exemplary values above, Γ = (52 − 45) / (52 + 45) ≈ 0.072. In practice, the effective reflection coefficient at abrupt segment boundaries may be even larger (e.g., Γ ≈ 0.15) due to parasitic effects, fringing fields, and geometric discontinuities at the segment edges that are not captured by the simple transmission line formula.
In the inventive structure, the impedance varies smoothly and continuously through the tapered transition region 136, following the taper profile function selected for the design (e.g., linear, exponential, or Klopfenstein). The impedance transitions gradually from 45 Ω at the edge of segment 132a to 52 Ω at the edge of segment 132b over the taper length L_taper. The reflection coefficient at any point within the taper is determined by the local rate of impedance change, which is small because the impedance changes gradually over a distance of 20–100 µm rather than abruptly.
For a Klopfenstein taper profile with L_taper = 50 µm, electromagnetic simulations predict that the maximum reflection coefficient within the passband (defined as frequencies up to 70 GHz) is less than 0.02, representing an improvement of approximately an order of magnitude compared to the conventional abrupt-junction design (Γ ≈ 0.15). This dramatic reduction in reflections translates directly into improved modulation bandwidth and frequency response flatness, as described below.
Modulation Bandwidth Results (Referring to FIG. 6)
FIG. 6 is a graph illustrating electro-optic frequency response (S21) measurements for modulators fabricated with the inventive process (solid line) and a conventional process (dashed line). The measurements were obtained from prototype devices fabricated on a 200 mm SOI wafer using the process flow described herein.
The modulator fabricated with the conventional process (abrupt-junction segmented electrode) exhibits a 3-dB electro-optic bandwidth of approximately 45 GHz. The frequency response shows a monotonically decreasing trend punctuated by ripples and dips attributable to microwave reflections at the electrode segment boundaries. These reflections create constructive and destructive interference patterns that manifest as ripple in the S21 response, with peak-to-peak ripple amplitude of approximately 2–3 dB in the 30–50 GHz frequency range. Above about 45 GHz, the S21 response falls below the −3 dB level relative to the low-frequency value.
The modulator fabricated with the inventive process (tapered-transition segmented electrode) exhibits a 3-dB electro-optic bandwidth exceeding 60 GHz. The frequency response is significantly smoother than that of the conventional design, with peak-to-peak ripple reduced to less than 0.5 dB across the entire measurement range (DC to 70 GHz). The improved bandwidth and reduced ripple are directly attributable to the reduction in microwave reflections at the electrode segment boundaries provided by the tapered impedance-matching regions.
The achieved bandwidth of greater than 60 GHz is sufficient for operation at 100 GBaud with PAM4 modulation (supporting 800G per lane) and for 64 GBaud with 16-QAM or higher-order coherent modulation formats (supporting 1.6T aggregate per module). The improved bandwidth therefore enables the use of the inventive modulator in next-generation 800G and 1.6T optical transceiver modules for data-center interconnect applications.
The improved bandwidth performance is attributed to two primary factors: (1) the reduced microwave reflections at electrode segment transitions, which allow the forward-propagating RF signal to be delivered efficiently to the full length of the electrode; and (2) the reduced microwave loss associated with the elimination of localized current-crowding and field-enhancement effects at abrupt segment boundaries.
Alternative Embodiments. While the above description has been made with reference to specific preferred embodiments, the invention is not limited thereto, and various alternative embodiments are contemplated within the scope of the appended claims.
In an alternative embodiment, the tapered impedance-matching regions may be formed using a multi-step (three or more) lithographic and deposition sequence rather than the two-step sequence described above. In this approach, additional lithographic masks with successively finer graded opening profiles are used, and additional metal deposition steps are performed, to create a more finely graded impedance taper. The multi-step approach provides greater control over the taper profile at the cost of additional process complexity.
In another alternative embodiment, the tapered impedance-matching regions are formed by selective electroplating through a resist mask with a graded seed layer. In this approach, a thin seed layer having a spatially varying thickness or surface activity is deposited in the transition region prior to photoresist application, and electroplating is performed through a conventional (non-graded) photoresist opening. The electroplating rate varies spatially due to the graded seed layer, producing the desired tapered metal thickness profile.
In another alternative embodiment, the inventive fabrication process is applied to a push-pull dual-drive MZM configuration, in which separate RF driving signals are applied to the two arms of the Mach-Zehnder interferometer. In this configuration, each arm has its own segmented traveling-wave electrode with tapered impedance-matching transitions, and the fabrication process described herein is applied to each electrode independently.
In another alternative embodiment, the inventive fabrication process is applied to a nested MZM configuration, also known as an IQ modulator, for coherent modulation applications. A nested MZM comprises two child MZMs (an in-phase (I) modulator and a quadrature (Q) modulator) nested within a parent MZM. The parent MZM provides a 90° optical phase offset between the I and Q paths. Each child MZM has its own segmented traveling-wave electrode structure, and the tapered impedance-matching fabrication process is applied to the electrode structures of both child MZMs.
In another alternative embodiment, the tapered impedance-matching region also incorporates a capacitively-loaded slow-wave structure for enhanced velocity matching. In this embodiment, the tapered metal region includes periodic or aperiodic capacitive loading elements (e.g., T-shaped or cross-shaped metal extensions from the signal electrode toward the ground electrodes) that increase the effective capacitance per unit length of the electrode transmission line, thereby reducing the RF propagation velocity to better match the optical group velocity. The tapered impedance-matching technique of the present invention is combined with the capacitive loading technique to simultaneously optimize both impedance matching and velocity matching.
In another alternative embodiment, the fabrication process is integrated into a standard silicon-photonics foundry CMOS back-end-of-line (BEOL) process flow. In this embodiment, the electrode fabrication steps described herein are performed using the same tools, materials, and process modules as the standard BEOL metal interconnect layers of the foundry process. For example, the first and second metal layers may be deposited using the foundry's standard copper damascene process, with the graded opening profile implemented using a gray-scale mask in the foundry's standard lithography tool. This integration enables high-volume manufacturing of the inventive electrode structure without the need for dedicated or specialized fabrication equipment.
In another alternative embodiment, the metal system comprises gold rather than aluminum or copper. Gold metallization provides lower resistivity and higher chemical stability, which may be advantageous for certain high-frequency applications, but is generally not compatible with standard CMOS processing. The inventive fabrication process may be applied with gold metallization in non-CMOS-compatible process flows, such as those used in III-V compound semiconductor or hybrid integration platforms.
In another alternative embodiment, the specific taper profile function is selected from among the linear, quadratic, exponential, and Klopfenstein profiles described above, or other profile functions known in the art, based on the specific performance requirements of the modulator design. The choice of taper profile involves a trade-off between taper length, bandwidth, and maximum passband reflection coefficient, and electromagnetic simulation tools are used to optimize the profile for each application.
It will be understood by those skilled in the art that the foregoing detailed description is illustrative only and that many modifications and variations are possible within the scope of the invention as defined by the appended claims.
CLAIMS
What is claimed is:
1. A method of fabricating a segmented traveling-wave electrode on a silicon-photonic substrate, the method comprising:
(a) providing a silicon-photonic substrate having a waveguide layer with at least one electro-optic phase-shifter region;
(b) depositing and patterning a first metal layer to form a plurality of discrete electrode segments over the phase-shifter region, the electrode segments being separated by gaps;
(c) forming a lithographic mask layer over the electrode segments, the mask layer having a graded opening profile in at least one gap region between adjacent electrode segments; and
(d) depositing a second metal layer through the graded opening to form a tapered impedance-matching region in the gap, the tapered impedance-matching region having a metal thickness that varies continuously from a first thickness proximate a first electrode segment to a second, different thickness proximate a second electrode segment;
wherein the tapered impedance-matching region provides a continuous impedance transition between the first and second electrode segments.
2. The method of claim 1, wherein the graded opening profile comprises a plurality of sub-resolution apertures having a spatially varying density or size.
3. The method of claim 1, wherein the graded opening profile is formed using a gray-scale lithographic mask.
4. The method of claim 1, wherein the first metal layer and the second metal layer comprise the same metal selected from the group consisting of aluminum, copper, and gold.
5. The method of claim 1, wherein the tapered impedance-matching region has a taper length of between 20 µm and 100 µm.
6. The method of claim 1, wherein the metal thickness in the tapered impedance-matching region varies according to a profile selected from the group consisting of a linear profile, a quadratic profile, and an exponential profile.
7. The method of claim 1, further comprising depositing a capping metal layer over the electrode segments and the tapered impedance-matching region.
8. The method of claim 1, wherein the silicon-photonic substrate comprises a silicon-on-insulator (SOI) wafer having a silicon device layer thickness of between 200 nm and 300 nm.
9. The method of claim 1, wherein the at least one electro-optic phase-shifter region comprises a PN junction formed by ion implantation.
10. The method of claim 1, wherein the plurality of discrete electrode segments comprises between 3 and 12 segments, each segment having a length of between 200 µm and 2 mm.
11. The method of claim 1, wherein the characteristic impedance of each electrode segment is between 25 Ω and 75 Ω, and the tapered impedance-matching region transitions continuously between the characteristic impedances of the adjacent segments.