UNITED STATES PATENT AND TRADEMARK OFFICE
NON-PROVISIONAL UTILITY PATENT APPLICATION UNDER 35 U.S.C. § 111(a)
APPLICATION TRANSMITTAL
Filing Date: January 29, 2024
Applicant / Assignee:
Optiwave Semiconductor Corp. A Delaware corporation 4710 Ridgeview Parkway, Suite 300 Santa Clara, CA 95054 EIN: 83-2947105
Entity Status: Small Entity (fewer than 500 employees; Optiwave Semiconductor Corp. currently employs approximately 185 employees and qualifies for small entity status under 37 C.F.R. § 1.27)
Inventors:
Correspondence Address:
Calderwood & Harkness LLP
Attn: Christy Bauer (Reg. No. 74,329)
555 California Street, 42nd Floor San Francisco, CA 94104 Telephone: (415) 555-7800 Facsimile: (415) 555-7801
Priority Claim: This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63/297,841, filed January 10, 2022, titled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture." This application is also related to International Application No. PCT/US2023/010612 (PCT Application A5), filed January 9, 2023.
Related Applications Cross-Reference Note: This application is a continuation-in-part of, or is otherwise related to, U.S. Application No. 17/672,204 (Sub-Family A1, filed January 9, 2023), and shares common subject matter with the following applications: PCT/US2023/010612 (A5); European Application No. EP 23 765 901.7 (C2); and Japanese Application No. JP 2024-542305 (C3). All related applications are assigned to Optiwave Semiconductor Corp.
Prepared and Filed Under: Pre-freeze budget authorization.
Drafted by: Christy Bauer, Reg. No. 74,329, Calderwood & Harkness LLP
Enclosures:
1. Specification (including Title, Cross-Reference to Related Applications, Background, Summary, Brief Description of the Drawings, and Detailed Description of the Preferred Embodiments)
2. Claims (20 total: 3 independent, 17 dependent)
3. Abstract of the Disclosure
4. Drawings (10 Figures: FIG. 1 through FIG. 10, with FIGS. 3A–3B and FIGS. 7A–7B)
5. Inventor Declaration / Oath (37 C.F.R. § 1.63)
6. Assignment
7. Power of Attorney
8. Application Data Sheet (ADS)
9. Fee Transmittal (Small Entity)
SPECIFICATION
THERMALLY-ENHANCED FLIP-CHIP PACKAGING ARCHITECTURE FOR MULTI-CHANNEL SILICON-PHOTONIC MACH-ZEHNDER MODULATOR ARRAYS
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 63/297,841, filed January 10, 2022 (expired January 10, 2023), titled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture," originally filed by Kessler & Morin LLP on behalf of Optiwave Semiconductor Corp. The disclosure of U.S. Provisional Application No. 63/297,841 is incorporated herein by reference in its entirety.
This application is related to the following co-pending United States patent applications, each of which is assigned to Optiwave Semiconductor Corp. and is incorporated herein by reference in its entirety:
(a) U.S. Non-Provisional Application No. 17/672,204, filed January 9, 2023, titled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture";
(b) U.S. Continuation Application No. 17/672,311, filed March 15, 2023;
(c) U.S. Continuation-in-Part Application No. 17/672,489, filed June 22, 2023;
(d) U.S. Non-Provisional Application No. 17/814,057, filed July 21, 2023, directed to electrode fabrication processes;
(e) International Application No. PCT/US2023/010584, filed January 9, 2023;
(f) International Application No. PCT/US2023/010612, filed January 9, 2023;
(g) European Application No. EP 23 765 901.7, entered July 8, 2023 (European regional phase of PCT/US2023/010612); and
(h) Japanese Application No. JP 2024-542305, entered July 8, 2023 (Japanese national phase of PCT/US2023/010612).
All of the foregoing applications are assigned to Optiwave Semiconductor Corp., a Delaware corporation, and the disclosures thereof are incorporated herein by reference in their respective entireties to the extent not inconsistent with the present disclosure.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable. The invention described herein was not made with government support, and no federal agency has rights in this invention.
FIELD OF THE INVENTION
The present invention relates generally to semiconductor photonics packaging, and more specifically to thermally-managed flip-chip packaging architectures for high-speed silicon-photonic integrated circuits (PICs) incorporating multi-channel Mach-Zehnder modulator (MZM) arrays. The invention is particularly directed to packaging solutions designed for 800G and 1.6T data-center optical transceiver applications that require the simultaneous management of high-frequency radio-frequency (RF) signal integrity, precision photonic waveguide coupling, and efficient thermal dissipation in densely integrated PIC modules.
The field of the invention encompasses the intersection of advanced semiconductor packaging technologies, silicon photonics integration, and thermal management engineering as applied to high-bandwidth optical communication systems. The invention addresses challenges that arise specifically in the context of fabless semiconductor design methodologies for silicon-photonics-based devices, wherein the photonic integrated circuit die is fabricated at a commercial silicon foundry and subsequently assembled into a multi-function package that must satisfy stringent electrical, optical, thermal, and mechanical performance requirements simultaneously.
More particularly, the invention is directed to flip-chip bonding architectures that employ spatially-graded conductive bump interconnects, embedded micro-channel thermal management structures, and passive optical alignment features integrated into a common interposer substrate platform. The packaging architecture disclosed herein is intended for use with silicon-photonic MZM arrays employing segmented traveling-wave electrode architectures operating at modulation bandwidths exceeding 100 GHz per lane, and is designed to support next-generation coherent and intensity-modulation direct-detection (IM-DD) transceiver module formats.
BACKGROUND OF THE INVENTION
Context of Data-Center Interconnect Technology
The rapid growth of hyperscale data centers, driven by the proliferation of cloud computing services, artificial intelligence (AI) training workloads, and machine learning (ML) inference clusters, has created an insatiable demand for higher-bandwidth optical interconnects. Current generation data-center interconnects operating at 400G per port are being superseded by 800G solutions, with 1.6T modules already in development and expected to reach volume deployment within the next product cycle. These bandwidth requirements are driven not only by the aggregate traffic demands of large-scale distributed computing, but also by the specific characteristics of AI/ML workloads, which exhibit highly bursty, all-to-all communication patterns that stress the capacity of every link in the network fabric.
Silicon-photonic integrated circuits have emerged as the leading technology platform for next-generation optical transceivers due to their compatibility with established CMOS fabrication infrastructure, their potential for monolithic integration of multiple photonic functions on a single die, and their favorable cost-scaling characteristics in high-volume production. Among the various photonic modulator architectures, multi-channel Mach-Zehnder modulator arrays utilizing segmented traveling-wave electrode designs offer a compelling combination of electro-optic bandwidth, linearity, and modulation efficiency that is well-suited to the PAM-4 and coherent modulation formats employed in 800G and 1.6T transceiver standards.
Overview of Silicon-Photonic Mach-Zehnder Modulator Technology
A Mach-Zehnder modulator operates by splitting an incoming optical signal into two waveguide arms, applying a differential phase shift between the arms through the electro-optic effect, and then recombining the two arms at an output coupler. The resulting interference between the two optical paths converts phase modulation into amplitude modulation. In silicon photonics implementations, the phase shift is typically achieved through the plasma dispersion effect, wherein the injection, depletion, or accumulation of free carriers in a silicon waveguide alters its effective refractive index.
To achieve the high modulation bandwidths required for 200 Gbaud (and beyond) per-lane operation, traveling-wave electrode architectures are employed. In a traveling-wave MZM, the RF drive co-propagates with the optical signal along the length of the modulator phase-shifter section, enabling velocity matching between the RF and optical waves. Segmented traveling-wave electrode designs, in which the electrode is divided into discrete segments with independent impedance-matching and bias-point control, offer further advantages in terms of bandwidth extension, drive voltage reduction, and process tolerance.
The broader technology landscape of silicon-photonic MZM arrays includes Optiwave Semiconductor Corp.'s core modulator architecture, which is the subject of the parent provisional application (U.S. Provisional Application No. 63/297,841) and the corresponding non-provisional application (U.S. Application No. 17/672,204). These related applications describe, inter alia, specific configurations of the segmented traveling-wave electrode geometry, the modulator phase-shifter design, and the associated driver circuit interfaces. The present invention is directed specifically to the packaging-level innovations that enable the high-performance operation of such modulator arrays in practical transceiver module implementations.
Thermal Management Challenges in PIC Packaging
As modulator arrays scale from four-channel to eight-channel and sixteen-channel configurations, with each channel operating at modulation rates of 200 Gbaud PAM-4 or higher, the thermal management challenges become increasingly severe. Multiple sources of heat generation are present in a high-speed MZM array, including:
(i) Joule heating in the traveling-wave electrodes, which carry high-frequency RF drive signals with peak currents on the order of tens of milliamperes per channel at frequencies exceeding 67 GHz;
(ii) Carrier-injection or carrier-depletion heating in the silicon waveguide phase-shifter sections, where the flow of electrical current through the p-n junction or p-i-n structure generates localized heat;
(iii) Optical absorption heating, particularly in regions of high optical intensity such as waveguide bends, couplers, and the modulator arms themselves; and
(iv) Resistive heating in the electrical interconnects, bond wires, or bump connections between the RF driver integrated circuit and the modulator electrodes.
The aggregate power dissipation of a modern 8-channel MZM array operating at full speed can reach 4 watts or more, concentrated in a die area of only a few square millimeters. The resulting thermal gradients across the modulator array have several deleterious effects on device performance. First, temperature-dependent changes in the silicon waveguide refractive index cause drift in the modulator bias point, degrading the modulation extinction ratio and increasing the bit error rate. Second, in wavelength-division multiplexed (WDM) systems that employ integrated wavelength-selective elements such as micro-ring resonators or arrayed waveguide gratings, thermal non-uniformity across the array causes differential wavelength drift among the channels, leading to crosstalk and increased power penalty. Third, thermal gradients induce mechanical stress through differential thermal expansion, which can cause polarization-dependent loss variations, waveguide birefringence changes, and, over time, fatigue-related reliability failures in the electrical interconnects.
Limitations of Conventional Packaging Approaches
Conventional packaging approaches for silicon-photonic integrated circuits suffer from several fundamental limitations that prevent them from meeting the performance requirements of next-generation 800G and 1.6T transceiver modules. These limitations may be summarized as follows:
(a) Excessive parasitic inductance at high RF frequencies. Traditional wire-bond interconnects between the driver IC and the modulator electrodes introduce parasitic inductance on the order of 0.5–1.0 nH per bond wire, which severely degrades the RF signal integrity at frequencies above 50 GHz. The resulting impedance discontinuity causes signal reflections, increased insertion loss, and degraded eye-diagram quality at 200 Gbaud PAM-4 data rates.
(b) Poor thermal conduction pathways. In conventional face-up (junction-up) packaging, the thermal path from the modulator active region to the heat sink passes through the full thickness of the silicon die (typically 300–750 µm), the die-attach material, and the package substrate. This thermal stack presents a cumulative thermal resistance that is often too high to maintain acceptable temperature uniformity across a multi-channel array.
(c) Mechanical stress-induced polarization-dependent loss. Edge-coupled packaging approaches that rely on butt-coupling of optical fibers to the PIC die facets are susceptible to mechanical stress at the fiber-to-chip interface, which can induce birefringence changes in the coupling region and cause polarization-dependent loss (PDL) variations. These variations are exacerbated by thermal cycling during normal transceiver operation.
(d) Incompatibility with high-volume automated assembly. Many existing silicon-photonic packaging approaches require active optical alignment during assembly, in which the fiber position is adjusted while monitoring the coupled optical power in real time. This active alignment process is inherently slow, requiring seconds to minutes per fiber channel, and is not compatible with the high-throughput automated assembly processes needed for cost-effective volume production of data-center transceivers.
Existing Art Deficiencies
Prior approaches to flip-chip packaging of photonic devices, while offering advantages over wire-bond packaging in terms of reduced parasitic inductance and improved thermal paths, have not successfully addressed the simultaneous requirements of RF impedance matching at the bump interconnect level, controlled thermal resistance from modulator active regions to the package substrate, and optical coupling alignment tolerances below 0.5 µm. Specifically, conventional flip-chip photonic packages typically employ uniform-pitch, uniform-diameter solder bump arrays that provide a single, fixed characteristic impedance at the interconnect. This fixed impedance creates an abrupt impedance discontinuity at the transition between the 50 Ω RF driver transmission line and the typically lower-impedance (25–35 Ω) loaded traveling-wave electrode of the modulator, resulting in significant RF reflections and bandwidth limitation.
Furthermore, conventional flip-chip packages for photonic devices typically rely on external heat sinks or thermoelectric coolers (TECs) attached to the package lid or base for thermal management, without integrating thermal management structures directly into the interposer substrate beneath the active regions. This approach results in unnecessarily long thermal paths and higher thermal resistance, particularly for the inner channels of a multi-channel array that are furthest from the package perimeter.
Certain prior art approaches to silicon-photonic MZM packaging with segmented electrodes, including designs disclosed in U.S. Patent No. 10,823,417 and U.S. Patent No. 11,105,662 (both assigned to Pinnacle Optics, Inc.), address aspects of the electrode architecture at the device level but do not disclose the specific packaging-level thermal management innovations of the present invention. In particular, the Pinnacle Optics patents do not disclose the combination of tapered impedance-matching bump interconnect arrays with embedded micro-channel heat sinks integral to the package substrate. The Pinnacle disclosures focus on the modulator electrode segmentation geometry and drive scheme, but are silent on the packaging-level implementation of impedance matching at the bump interconnect and the integration of micro-channel thermal management structures within the interposer.
Need in the Art
In view of the foregoing limitations of the prior art, there is a clear need for a packaging architecture that provides:
(1) Low-parasitic RF interconnects compatible with traveling-wave electrode modulator designs, particularly those employing tapered impedance-matching features that provide a gradual, broadband impedance transition from the driver IC output to the modulator electrode input;
(2) Efficient thermal dissipation integrated into the package substrate, positioned directly beneath the modulator active regions to minimize thermal resistance and ensure temperature uniformity across all channels; and
(3) Precision optical coupling using passive alignment structures that are compatible with flip-chip assembly processes and that achieve sub-micron alignment tolerances without the need for active alignment during manufacturing.
The present invention addresses these needs by providing a thermally-enhanced flip-chip packaging architecture that simultaneously solves the RF, thermal, and optical coupling challenges of multi-channel silicon-photonic MZM array packaging.
SUMMARY OF THE INVENTION
The present invention provides a thermally-enhanced flip-chip packaging architecture for multi-channel silicon-photonic Mach-Zehnder modulator (MZM) arrays. The packaging architecture integrates several innovative features into a unified platform that addresses the simultaneous challenges of high-frequency RF signal integrity, efficient thermal dissipation, and precision optical fiber coupling in densely integrated photonic integrated circuit (PIC) modules.
In one aspect, the invention provides a flip-chip packaging assembly for a silicon-photonic integrated circuit comprising a photonic integrated circuit die, an interposer substrate, a tapered impedance-matching bump array, embedded micro-channel thermal management structures, and passive optical alignment features.
In another aspect, the invention provides a method of assembling a thermally-enhanced flip-chip package for a silicon-photonic modulator array.
In yet another aspect, the invention provides an optical transceiver module incorporating the thermally-enhanced flip-chip packaged modulator assembly.
The key innovative features of the present invention include the following:
1. Tapered Impedance-Matching Bump Array. The packaging architecture employs a spatially-graded array of conductive bumps positioned along the traveling-wave electrode feed lines of each modulator channel. The conductive bumps, which are preferably copper pillar bumps, have controlled diameter variation from approximately 25 µm at the RF input end to approximately 45 µm at the modulator electrode connection end. This graduated bump geometry provides a continuous impedance matching transition from the approximately 50 Ω characteristic impedance of the RF driver IC transmission lines to the approximately 25–35 Ω loaded impedance of the segmented traveling-wave electrodes of the MZM. The taper profile may be linear, exponential, or follow a Klopfenstein-type profile to achieve broadband impedance matching with minimal passband ripple. This tapered impedance-matching bump array design is coordinated with, and complementary to, the design-around claim strategy of parent application A1 (U.S. Application No. 17/672,204) relative to the Pinnacle Optics electrode-segmentation geometry, providing packaging-level implementation of the impedance-matching concept.
2. Embedded Micro-Channel Heat Sink in Package Substrate. The interposer substrate incorporates a network of micro-fluidic or micro-convective channels fabricated directly beneath the modulator active regions of the PIC die. The channels have cross-sectional dimensions of 50–200 µm in width and 100–400 µm in depth, and are designed to provide a thermal resistance below 0.5 K/W from the modulator junction to the coolant or heat-dissipation surface. In a preferred embodiment, the micro-channels are hermetically sealed and partially filled with a dielectric fluid (such as Greaves & Co. 7100 or equivalent) to form a passive micro-heat-pipe structure that operates without the need for an external pump or active fluid circulation system.
3. Passive-Alignment Optical Coupling Structures. Lithographically-defined V-groove and pedestal alignment features are formed on the interposer substrate surface, enabling sub-micron alignment of optical fiber arrays to the PIC edge couplers or grating couplers during the flip-chip bonding and assembly process. These passive alignment structures eliminate the need for active optical alignment during manufacturing, enabling high-throughput automated assembly compatible with volume production requirements.
4. Differential Thermal Expansion Compensation Layer. An intermediate compliant layer, such as a polymer underfill with an engineered coefficient of thermal expansion (CTE) of 8–12 ppm/°C, is positioned between the PIC die and the interposer substrate. This compensation layer accommodates the CTE mismatch between the silicon PIC die (CTE approximately 2.6 ppm/°C) and the ceramic or organic interposer substrate (CTE typically 5.8–17 ppm/°C, depending on the substrate material), thereby preventing thermomechanical stress-induced failures in the bump interconnects during thermal cycling.
The thermally-enhanced flip-chip packaging architecture of the present invention enables the operation of 8×200 Gbaud PAM-4 modulator arrays, providing an aggregate data throughput of 1.6 Tbit/s, with less than 2°C temperature variation across all modulator channels under full operating power conditions. The tapered impedance-matching bump array achieves RF insertion loss below 1.5 dB at 67 GHz at each bump interconnect, representing a substantial improvement over conventional wire-bond and uniform-bump interconnect approaches. The passive optical alignment structures enable optical coupling loss below 1.0 dB per channel, including contributions from alignment tolerance and mode-field mismatch.
The packaging architecture of the present invention is designed for integration into 800G and 1.6T pluggable optical transceiver modules in standard form factors such as QSFP-DD800 and OSFP, as well as co-packaged optics (CPO) configurations for AI/ML cluster networking applications.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
FIG. 1 is a perspective exploded view of the thermally-enhanced flip-chip package assembly according to an embodiment of the present invention, showing the PIC die, the tapered impedance-matching bump array, the interposer substrate with embedded micro-channels, and the fiber alignment structures.
FIG. 2 is a cross-sectional view taken along the line A-A′ of FIG. 1, showing the thermal conduction path from the MZM active region through the conductive bumps, through the interposer substrate, and to the heat sink.
FIG. 3A is a top plan view of the tapered impedance-matching bump array layout according to an embodiment of the present invention, showing graduated bump diameters along the traveling-wave electrode feed line from the RF driver connection point to the modulator electrode termination.
FIG. 3B is a detail cross-sectional view of a single impedance-matching bump according to an embodiment of the present invention, showing the copper pillar, solder cap, and under-bump metallization (UBM) layers.
FIG. 4 is a schematic cross-sectional view of the embedded micro-channel heat sink within the interposer substrate according to an embodiment of the present invention, showing the channel geometry, inlet/outlet manifolds, and the spatial relationship of the channels to the modulator active regions positioned above.
FIG. 5 is a plan view of the passive-alignment optical coupling structure according to an embodiment of the present invention, showing the V-groove array and pedestal registration features formed on the interposer substrate.
FIG. 6 is a thermal simulation contour map of an 8-channel MZM array packaged according to an embodiment of the present invention, showing the temperature distribution under full operating power conditions with a total power dissipation of 4 W.
FIG. 7A is a graph showing RF S-parameter (S21, insertion loss) simulation results comparing a conventional wire-bond interconnect versus the tapered impedance-matching bump array of the present invention, over a frequency range from DC to 100 GHz.
FIG. 7B is a graph showing return loss (S11) simulation results comparing the conventional wire-bond interconnect versus the tapered impedance-matching bump array of the present invention, over the same frequency range.
FIG. 8 is a process flow diagram illustrating the fabrication and assembly sequence for the thermally-enhanced flip-chip package according to an embodiment of the present invention.
FIG. 9 is a schematic view showing the integration of the packaged MZM module into a QSFP-DD800 or OSFP transceiver module format according to an embodiment of the present invention.
FIG. 10 is a cross-sectional view showing the differential thermal expansion compensation layer positioned between the PIC die and the interposer substrate according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following detailed description sets forth specific embodiments of the thermally-enhanced flip-chip packaging architecture of the present invention. These embodiments are intended to be illustrative rather than limiting, and it will be apparent to those of ordinary skill in the art that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the invention as defined by the appended claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by those of ordinary skill in the art that the present invention may be practiced without some or all of these specific details. In other instances, well-known process operations and device structures have not been described in detail in order to avoid unnecessarily obscuring the present invention.
As used herein, the terms "approximately," "about," and "substantially" refer to values that are within ±10% of the stated value unless otherwise indicated. The term "comprising" is intended to be open-ended, meaning that the recited elements are included but other elements may also be present. Directional terms such as "above," "below," "top," "bottom," and the like are used for convenience and refer to the orientations shown in the drawings, and are not intended to limit the scope of the invention to any particular spatial orientation.
1. Overview of the Package Architecture. Referring now to FIGS. 1 and 2, the thermally-enhanced flip-chip package assembly 100 according to a preferred embodiment of the present invention will be described. The package assembly 100 comprises a photonic integrated circuit (PIC) die 110, an interposer substrate 120, a tapered impedance-matching bump array 130, an embedded micro-channel heat sink structure 140, passive optical alignment structures 150, and a differential thermal expansion compensation layer 160.
The PIC die 110 is a silicon-on-insulator (SOI) photonic chip fabricated by a commercial silicon photonics foundry using a standard SOI process with a silicon device layer thickness of approximately 220 nm on a buried oxide (Box) layer of approximately 2 µm. The PIC die 110 contains an array of N Mach-Zehnder modulators 112, where N is preferably 4, 8, or 16, depending on the target aggregate data rate of the transceiver module. Each Mach-Zehnder modulator 112 comprises a pair of waveguide arms 114a, 114b with integrated phase-shifter sections, input and output multimode interference (MMI) couplers 116, and segmented traveling-wave electrodes 118 disposed along the phase-shifter sections. The traveling-wave electrodes 118 are fabricated in a multi-level metal stack on the PIC die 110 and are designed to co-propagate the RF drive signal with the optical signal to achieve velocity matching at the target modulation frequency.
In the preferred embodiment, the PIC die 110 has overall dimensions of approximately 5 mm × 8 mm × 0.3 mm (width × length × thickness) for an 8-channel configuration, with the eight MZM channels arranged in a parallel, side-by-side configuration with a channel pitch of approximately 500 µm. The PIC die 110 may further include integrated photodetectors for monitoring optical power, integrated heaters for wavelength tuning of associated ring resonators or wavelength filters, and waveguide routing structures for connecting the modulator array to input/output optical coupling ports at the die edge.
The PIC die 110 is mounted in a flip-chip configuration, with the active surface (i.e., the surface containing the waveguides, modulators, and electrodes) facing downward toward the interposer substrate 120. This face-down orientation places the modulator active regions in close thermal proximity to the interposer substrate 120 and its embedded thermal management structures, minimizing the thermal resistance between the heat-generating regions and the cooling medium. The flip-chip orientation also enables the shortest possible electrical path between the bump interconnects and the modulator electrodes, reducing parasitic inductance and capacitance.
The interposer substrate 120 serves as the central structural and functional element of the package assembly 100, providing mechanical support, electrical redistribution, thermal management, and optical alignment functions. The interposer substrate 120 may be fabricated from one of several materials, including single-crystal silicon, low-temperature co-fired ceramic (LTCC), or high-performance organic laminate, depending on the specific performance and cost requirements of the target application. In the preferred embodiment, the interposer substrate 120 is a silicon interposer with overall dimensions of approximately 15 mm × 20 mm × 1.0 mm, providing sufficient area for the PIC die 110, associated RF redistribution traces, and the passive optical alignment structures.
The interposer substrate 120 includes a multi-layer metallization stack comprising alternating layers of patterned copper traces and dielectric insulation, providing controlled-impedance RF signal routing from the package input/output pads to the bump interconnect locations beneath the PIC die 110. The metallization stack also provides ground planes for RF shielding between adjacent modulator channels and DC power distribution traces for modulator bias and heater control.
Embedded within the body of the interposer substrate 120 are the micro-channel heat sink structures 140, which will be described in detail in Section 3 below. The micro-channels are positioned directly beneath the modulator active regions of the PIC die 110 to provide the shortest possible thermal path from the heat sources to the cooling medium.
Formed on the upper surface of the interposer substrate 120, adjacent to the PIC die mounting area, are the passive optical alignment structures 150, which will be described in detail in Section 4 below. These structures provide mechanical registration features for precision alignment of optical fiber arrays to the PIC die 110 during assembly.
The complete package assembly 100, comprising the PIC die 110 bonded to the interposer substrate 120 with the intervening bump array 130 and underfill 160, is mounted on a printed circuit board (PCB) 170 or a flexible circuit that connects the package to the host transceiver electronics. The PCB 170 carries the DSP (digital signal processor) and driver IC, which provide the high-speed electrical signals to the MZM array through the flip-chip package. A heat sink 180, which may be a passive heat spreader or an active thermoelectric cooler, is attached to the exposed backside (top surface in the flip-chip orientation) of the PIC die 110 or to the bottom surface of the interposer substrate 120, depending on the thermal design configuration.
2. Tapered Impedance-Matching Bump Array. Referring now to FIGS. 3A and 3B, the tapered impedance-matching bump array 130 according to a preferred embodiment of the present invention will be described in detail.
The bump array 130 comprises a plurality of conductive bumps 132 arranged in a linear or quasi-linear pattern along each MZM RF feed line on the PIC die 110. For an 8-channel MZM array, there are eight independent bump array rows, one associated with each modulator channel, plus additional bumps for ground connections, DC bias lines, and control signals. Each bump array row comprises a signal line of bumps flanked by ground bumps in a ground-signal-ground (GSG) or ground-signal-ground-signal-ground (GSGSG) differential configuration, depending on whether the modulator is driven in single-ended or differential mode.
A key feature of the bump array 130 is that the diameters of the conductive bumps 132 vary systematically along the length of each feed line. Specifically, the bump diameter varies monotonically from a first diameter d₁ at the RF input end of the feed line (i.e., the end connected to the RF driver IC transmission line) to a second diameter d₂ at the MZM electrode connection end. In the preferred embodiment, the first diameter d₁ is approximately 25 µm and the second diameter d₂ is approximately 45 µm, although values in the ranges of 20–30 µm and 40–50 µm, respectively, are contemplated within the scope of the invention.
The variation in bump diameter along the feed line creates a corresponding variation in the characteristic impedance of the bump interconnect region. Smaller-diameter bumps present a higher impedance due to their higher inductance-to-capacitance ratio, while larger-diameter bumps present a lower impedance. By carefully controlling the bump diameter profile, the bump array 130 provides a gradual, continuous impedance transition from a first characteristic impedance Z₁ at the RF input end to a second characteristic impedance Z₂ at the modulator electrode end. In the preferred embodiment, Z₁ is approximately 50 Ω, matching the characteristic impedance of the RF driver IC output transmission lines, and Z₂ is approximately 25–35 Ω, matching the loaded characteristic impedance of the segmented traveling-wave electrodes of the MZM.
The taper profile, i.e., the mathematical function describing how the bump diameter (or equivalently, the characteristic impedance) varies as a function of position along the feed line, may be selected from several known taper functions in transmission line theory. In a first embodiment, the taper profile is linear, meaning that the bump diameter increases at a constant rate along the feed line. In a second embodiment, the taper profile is exponential, providing a constant fractional impedance change per unit length, which offers improved broadband matching compared to the linear taper. In a third and preferred embodiment, the taper profile follows a Klopfenstein taper design, which is known in the art to provide the optimum impedance match (minimum passband ripple) for a given taper length and impedance ratio. The Klopfenstein taper profile provides an impedance variation described by:
ln Z(x) = ½ ln(Z₁Z₂) + (Γ₀/cosh A) · A² φ(2x/L - 1, A)
where Z(x) is the impedance at position x along the taper of length L, Γ₀ is the reflection coefficient at zero frequency, A is a parameter that controls the passband ripple level, and φ is a modified Chebyshev function. The specific values of these parameters are selected through electromagnetic simulation to optimize the broadband matching performance for the target frequency range of DC to 100 GHz.
The bump pitch, i.e., the center-to-center spacing between adjacent bumps along the feed line, also varies along the taper. At the high-impedance (small-diameter) end, the bump pitch is approximately 60 µm, while at the low-impedance (large-diameter) end, the bump pitch increases to approximately 120 µm. This pitch variation is coordinated with the diameter variation to achieve the desired impedance profile while maintaining adequate mechanical support and solder joint reliability.
Referring specifically to FIG. 3B, each individual conductive bump 132 in the preferred embodiment comprises a copper pillar 134 formed on an under-bump metallization (UBM) stack 136, and capped with a solder cap 138. The UBM stack 136, which provides adhesion, barrier, and wetting functions, comprises a sequence of thin-film metal layers deposited on the aluminum or copper bond pad of the PIC die 110. In the preferred embodiment, the UBM stack 136 comprises, in order from the PIC die pad upward:
(i) A titanium (Ti) adhesion and barrier layer, with a thickness of approximately 0.1 µm (100 nm);
(ii) A copper (Cu) seed and conduction layer, with a thickness of approximately 5.0 µm;
(iii) A nickel (Ni) barrier and wetting layer, with a thickness of approximately 2.0 µm; and
(iv) A gold (Au) oxidation protection layer, with a thickness of approximately 0.5 µm.
The copper pillar 134 is electroplated on top of the UBM stack 136 to a height of approximately 30–50 µm, with the diameter of the pillar corresponding to the design diameter at that position along the taper. The solder cap 138, formed on top of the copper pillar 134, comprises a tin-silver (Sn-Ag, SAC305 composition: Sn-3.0%Ag-0.5%Cu) alloy with a thickness of approximately 15–25 µm. In an alternative embodiment, an indium (In)-based solder is used for the solder cap 138 to enable lower-temperature bonding (150–180°C versus 250–280°C for SAC305), which may be preferred for temperature-sensitive photonic devices.
The tapered impedance-matching bump array 130 of the present invention is distinguished from conventional uniform-pitch, uniform-diameter bump arrays used in prior flip-chip photonic packages. Conventional bump arrays provide a fixed characteristic impedance that typically does not match either the driver IC output impedance or the modulator electrode impedance, resulting in a double impedance discontinuity (at the driver-to-bump and bump-to-modulator transitions) and significant RF reflections. The tapered design of the present invention eliminates these discontinuities by providing a smooth, continuous impedance transition across the entire bump interconnect region.
Furthermore, the tapered impedance-matching bump array 130 provides a packaging-level implementation of the tapered impedance-matching concept that is also claimed at the device level in related application U.S. Application No. 17/672,204 (Sub-Family A1). While the related application addresses the impedance matching within the segmented traveling-wave electrode structure on the PIC die itself, the present invention extends the impedance-matching concept to the packaging interconnect level, ensuring end-to-end impedance continuity from the driver IC through the package interconnect to the modulator electrode.
3. Embedded Micro-Channel Heat Sink. Referring now to FIG. 4, the embedded micro-channel heat sink structure 140 according to a preferred embodiment of the present invention will be described in detail.
The micro-channel heat sink structure 140 comprises a plurality of micro-channels 142 fabricated within the body of the interposer substrate 120, positioned directly beneath the modulator active regions of the PIC die 110. The micro-channels 142 are connected at their ends to inlet and outlet manifold structures 144 that distribute and collect the heat-transfer medium.
The micro-channels 142 are fabricated using processes appropriate to the interposer substrate material. For a silicon interposer, the micro-channels 142 are formed by deep reactive ion etching (DRIE) using the Bosch process, which provides vertical sidewalls and high aspect-ratio channels with excellent dimensional control. For an LTCC ceramic interposer, the micro-channels 142 are formed by punching or laser-cutting channel patterns in individual green-tape layers prior to lamination and co-firing, a process that allows complex three-dimensional channel geometries to be created through appropriate stacking of patterned layers.
The micro-channels 142 have a width in the range of 50 µm to 200 µm, a depth in the range of 100 µm to 400 µm, and inter-channel wall thickness in the range of 30 µm to 100 µm. In the preferred embodiment, the channels have a width of approximately 100 µm, a depth of approximately 200 µm, and a wall thickness of approximately 50 µm, providing a channel aspect ratio of approximately 2:1 (depth:width) that balances thermal performance, structural integrity, and fabrication yield.
The channel layout may follow several configurations. In a first embodiment, the channels are arranged in a parallel straight configuration, with multiple straight channels running parallel to the length of the MZM phase-shifter sections. In a second embodiment, the channels follow a serpentine configuration, with a single continuous channel that winds back and forth beneath the modulator active regions, providing more uniform cooling at the expense of increased pressure drop. In a third embodiment, a combination of parallel and serpentine sections is used, with parallel channels beneath each individual modulator channel and serpentine manifold connections between them.
In the preferred passive cooling configuration, the micro-channels 142 are hermetically sealed within the interposer substrate 120 and partially filled with a dielectric heat-transfer fluid 146. The sealing is accomplished by bonding a cover layer (e.g., a silicon cap wafer or glass layer) over the open channel faces after the channels are etched and the fluid is introduced. The dielectric fluid 146 is preferably a fluorinated heat-transfer fluid such as 3M Greaves & Co. 7100 (methoxy-nonafluorobutane, boiling point 61°C at 1 atm) or equivalent, selected for its excellent dielectric properties, low surface tension (which promotes wetting and capillary action in the micro-channels), environmental compatibility, and chemical inertness with respect to the interposer substrate and metallization materials.
In this passive configuration, the micro-channels 142 operate as micro-heat-pipes. Heat generated in the modulator active regions of the PIC die 110 is conducted through the bump interconnects 132 and the thin silicon layer between the channel ceiling and the interposer surface to the dielectric fluid 146. The fluid absorbs the heat, and in regions of highest temperature, may undergo localized boiling (two-phase heat transfer), which greatly enhances the heat-transfer coefficient. The vapor generated by boiling migrates along the channels to cooler regions, where it condenses and releases its latent heat. The condensed liquid returns to the hot regions by capillary action, completing the heat-pipe cycle without the need for any external pump or active circulation system.
In an alternative active cooling configuration, the micro-channels 142 are connected to an external micro-pump and heat exchanger (radiator) through fluidic ports formed in the interposer substrate 120. In this configuration, deionized water or a fluorinated fluid is pumped continuously through the channels, providing forced convective cooling. The active cooling configuration offers higher heat-removal capacity and is preferred for higher-power applications such as 16-channel MZM arrays with total power dissipation exceeding 8 W.
The thermal performance of the embedded micro-channel heat sink 140 has been characterized through both analytical modeling and three-dimensional finite-element thermal simulation. The thermal resistance from the MZM junction (defined as the hottest point in the modulator phase-shifter section) to the heat-sink surface (defined as the external surface of the interposer substrate opposite the PIC die) is less than or equal to 0.5 K/W per modulator channel for the passive heat-pipe configuration. This low thermal resistance enables the package to maintain a temperature variation of less than 2°C across all eight channels of an 8-channel MZM array operating at a per-channel dissipation of approximately 0.5 W (4 W total for eight channels).
Referring to FIG. 6, the thermal simulation contour map shows the temperature distribution across the 8-channel MZM array under full operating power conditions. The simulation assumes a total power dissipation of 4 W distributed evenly across eight channels, with ambient temperature of 25°C and natural convection on the exposed package surfaces. The maximum junction temperature rise is approximately 12°C above ambient (i.e., maximum junction temperature of approximately 37°C), and the temperature variation between the hottest and coolest channels is less than 2°C. This level of thermal uniformity is sufficient to maintain modulation extinction ratio and wavelength stability within acceptable limits for 800G and 1.6T transceiver applications.
4. Passive-Alignment Optical Coupling Structures. Referring now to FIG. 5, the passive-alignment optical coupling structures 150 according to a preferred embodiment of the present invention will be described in detail.
The passive-alignment optical coupling structures 150 are formed on the upper surface of the interposer substrate 120, in a region adjacent to the PIC die mounting area and aligned with the optical input/output ports of the PIC die 110. The structures 150 comprise two primary components: a V-groove array 152 and pedestal registration features 154.
The V-groove array 152 comprises a plurality of V-shaped grooves etched into the surface of the silicon interposer substrate 120. For a silicon interposer, the V-grooves are formed by anisotropic wet etching using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) solutions, which etch the (100) crystal planes of silicon much faster than the (111) planes. The resulting V-grooves have sidewalls defined by the (111) crystal planes, which are oriented at an angle of 54.74° relative to the (100) substrate surface. This crystal-plane-defined geometry provides angular accuracy that is determined by the crystallographic structure of the silicon and is therefore inherently reproducible to sub-micron tolerances.
Each V-groove in the array 152 is sized to receive and mechanically register a single-mode optical fiber (e.g., Ashgrove Partners LLC SMF-28 Ultra or equivalent, with a cladding diameter of 125 µm). The V-groove width at the substrate surface is approximately 180 µm, and the V-groove depth is approximately 90 µm, such that a 125 µm diameter fiber resting in the groove is centered at a height of approximately 63 µm above the substrate surface. The V-groove pitch matches the fiber pitch of the target fiber array or ribbon assembly, which is typically 127 µm or 250 µm depending on the fiber count and ribbon format.
The pedestal registration features 154 are lithographically-defined structures (pillars, ridges, or recesses) formed on the interposer substrate 120 that mate with corresponding features on the edge of the PIC die 110 or on a separate fiber-array substrate. The pedestal features provide positional registration in the X (lateral), Y (longitudinal), and Z (vertical) directions, enabling the optical fiber cores to be aligned with the PIC waveguide coupling ports to an accuracy of ±0.3 µm in each axis. In the preferred embodiment, the pedestal features 154 comprise pairs of raised silicon pillars with precisely controlled heights and lateral positions, which engage with recesses or alignment marks etched into the PIC die edge. The combination of the V-groove fiber registration and the pedestal die-to-interposer registration provides a purely passive alignment system that achieves the required sub-micron coupling accuracy without the need for active optical monitoring during assembly.
The passive optical alignment structures 150 may be configured for either edge coupling or grating coupling to the PIC die 110. In the edge-coupling configuration, the fibers are aligned horizontally (parallel to the substrate surface) to waveguide facets exposed at the edge of the PIC die 110 or at edge couplers (such as spot-size converters or inverse tapers) that are designed to expand the waveguide mode field to match the fiber mode field. In the grating-coupling configuration, the fibers are aligned vertically (perpendicular or at a slight angle to the substrate surface) to grating couplers fabricated on the PIC die 110. Because the PIC die is mounted face-down in the flip-chip configuration, grating coupling in this orientation requires through-substrate grating designs in which the grating is designed to couple light through the silicon substrate and the buried oxide layer from the top (backside) surface of the PIC die.
The target optical coupling loss for the passive-alignment optical coupling structures 150 is less than 1.0 dB per channel, including contributions from alignment tolerance (estimated at 0.2–0.4 dB for ±0.3 µm misalignment), mode-field mismatch between the fiber and the PIC waveguide coupler (estimated at 0.3–0.5 dB for a well-designed spot-size converter), and Fresnel reflection at the fiber-to-air and air-to-chip interfaces (estimated at 0.1–0.2 dB with anti-reflection coatings).
5. Differential Thermal Expansion Compensation Layer. Referring now to FIG. 10, the differential thermal expansion compensation layer 160 according to a preferred embodiment of the present invention will be described in detail.
The compensation layer 160 is a compliant underfill material that is applied to fill the gap between the PIC die 110 and the interposer substrate 120 after the flip-chip bonding operation. The compensation layer 160 surrounds and encapsulates the conductive bumps 132 of the tapered impedance-matching bump array 130, providing both mechanical support and environmental protection for the bump interconnects.
The critical material properties of the compensation layer 160 are its coefficient of thermal expansion (CTE) and its elastic modulus (Young's modulus). The CTE of the compensation layer 160 is engineered to be intermediate between the CTE of the PIC die material (silicon, approximately 2.6 ppm/°C) and the CTE of the interposer substrate material. For a silicon interposer (CTE approximately 2.6 ppm/°C), the CTE mismatch between the PIC die and the interposer is minimal, and the compensation layer primarily serves as bump encapsulant and environmental protection. For LTCC ceramic interposers (CTE approximately 5.8 ppm/°C) or organic laminate interposers (CTE approximately 14–17 ppm/°C), the CTE mismatch is significant, and the compensation layer 160 plays a critical role in absorbing the differential thermal strain and preventing bump fatigue failure.
In the preferred embodiment, the compensation layer 160 has an engineered CTE of 8–12 ppm/°C and a Young's modulus of 3–8 GPa after curing. This combination of moderate CTE and moderate modulus provides an effective stress buffer between the low-CTE silicon PIC die and the higher-CTE interposer substrate. The CTE of the underfill material is controlled through the selection of the base polymer resin (e.g., epoxy or benzoxazine) and the filler type and loading (e.g., silica micro-particles at 60–70% by weight), while the modulus is controlled through the crosslink density and the filler loading.
The compensation layer 160 may be applied by one of two methods. In the first method (capillary flow underfill), the underfill material is dispensed in liquid form along one or more edges of the PIC die 110 after flip-chip bonding, and is drawn into the gap between the die and the interposer by capillary action. The underfill is then cured by heating to approximately 150°C for 30–60 minutes. In the second method (pre-applied wafer-level underfill), the underfill material is applied to the PIC wafer or the interposer wafer in the form of a non-conductive film (NCF) before dicing and flip-chip bonding. During the thermocompression bonding process, the NCF is reflowed by the bonding heat and fills the gap between the die and the interposer simultaneously with the solder reflow, eliminating the need for a separate underfill dispensing step.
The compensation layer 160 must satisfy the following reliability requirement: the packaged assembly must survive more than 1,000 thermal cycles over the temperature range of −40°C to +85°C (per JEDEC standard JESD22-A104) without evidence of bump crack initiation, solder joint open circuit, or underfill delamination from the PIC die or interposer substrate surfaces. This reliability target is verified through cross-sectional analysis, acoustic microscopy, and electrical continuity testing of qualification lots.
6. RF Redistribution and Signal Routing. The interposer substrate 120 includes a multi-layer RF redistribution network that connects the tapered impedance-matching bump array 130 to the package-level input/output pads that interface with the transceiver PCB. The RF redistribution traces are designed as controlled-impedance transmission lines, implemented in either stripline (traces sandwiched between two ground planes within the interposer metallization stack) or retriptrip (traces on the top surface of the interposer with a ground plane below) configurations.
The characteristic impedance of the RF redistribution traces is controlled to 50 Ω ± 2 Ω through precise specification of the trace width, dielectric thickness, and dielectric constant of the insulating layers. For a silicon interposer with silicon dioxide interlayer dielectric (dielectric constant approximately 3.9), a 50 Ω retriptrip trace width is approximately 25 µm for a 15 µm dielectric thickness. For an LTCC interposer with a dielectric constant of approximately 7.8, the corresponding trace width is approximately 15 µm.
Ground planes are integrated into the interposer metallization stack to provide RF shielding between adjacent modulator channels. In the preferred embodiment, a continuous ground plane layer is positioned between the RF signal traces and the micro-channel heat sink structures, providing both electrical shielding and a thermal conduction path from the bumps to the heat sink. The ground-plane metallization also serves as an electromagnetic shield to prevent crosstalk between adjacent channels. The target channel-to-channel RF isolation is greater than 30 dB at 67 GHz, which is verified through electromagnetic simulation of the interposer layout and validated through S-parameter measurements on fabricated interposers.
The RF redistribution network also includes DC bias traces for the modulator bias-point control (typically requiring ±3 V at currents of a few milliamperes) and heater control traces (for integrated thermo-optic phase trimmers, typically requiring up to 50 mA per heater at voltages up to 3 V). These DC traces are routed on separate metallization layers from the RF signal traces to minimize interference, and are decoupled with integrated bypass capacitors formed in the interposer metallization stack.
7. Fabrication and Assembly Process. Referring now to FIG. 8, the fabrication and assembly process for the thermally-enhanced flip-chip package according to a preferred embodiment of the present invention will be described. The process comprises the following sequential steps:
Step 1: Interposer Substrate Fabrication. The interposer substrate 120 is fabricated from a silicon wafer (for a silicon interposer embodiment) or from LTCC green-tape sheets (for a ceramic interposer embodiment). For the silicon interposer embodiment, the fabrication process includes:
(a) Micro-channel etching: The micro-channels 142 are etched into the backside of the silicon wafer using DRIE (deep reactive ion etching) with the Bosch process. A photolithographically-defined hard mask (e.g., silicon dioxide or silicon nitride) defines the channel geometry. The etch depth is controlled to achieve the target channel depth of 100–400 µm.
(b) Metallization: The multi-layer metallization stack is formed on the front side of the silicon wafer using standard thin-film deposition (sputtering or evaporation) and electroplating processes. The metallization stack includes the RF redistribution traces, ground planes, DC bias traces, and bond pad landing areas for the bump interconnects.
(c) V-groove formation: The V-grooves for optical fiber alignment are etched into the front surface of the silicon wafer using anisotropic wet etching in KOH or TMAH. A silicon nitride hard mask defines the V-groove locations and widths. The etch is self-terminating when the (111) crystal planes are fully exposed.
(d) Pedestal formation: The pedestal registration features are formed by photolithographic patterning and etching (either wet or dry) of the silicon surface in the same or a subsequent lithography step.
(e) Dicing: The completed interposer wafer is diced into individual interposer substrates.
Step 2: PIC Die Preparation. The PIC die 110, which is fabricated at a commercial silicon photonics foundry, is prepared for flip-chip bonding as follows:
(a) UBM deposition: The under-bump metallization stack (Ti/Cu/Ni/Au at thicknesses of 0.1/5.0/2.0/0.5 µm) is deposited on the bond pads of the PIC die using sputtering through a photolithographically-defined lift-off or etch mask.
(b) Copper pillar bump plating: Copper pillar bumps are electroplated on top of the UBM stack through a thick-film photoresist mold. Critically, the photoresist mold is designed with graduated openings corresponding to the tapered bump diameter profile, such that each bump is plated to the correct diameter for its position along the impedance-matching taper. The bump height is controlled by the plating time and current density.
(c) Solder cap plating: The solder cap (Sn-Ag SAC305 or In-based solder) is electroplated on top of the copper pillars, again through a photoresist mold that defines the cap diameter.
(d) Photoresist stripping and UBM seed layer etching: The plating mold is stripped, and the exposed UBM seed layer between bumps is removed by wet or dry etching.
(e) Solder reflow (optional): The solder caps may be reflowed to form spherical caps, which improve the self-alignment behavior during flip-chip bonding.
(f) Dicing: If the PIC wafer has not already been diced by the foundry, it is diced into individual PIC die at this stage.
Step 3: Flip-Chip Thermocompression Bonding. The PIC die 110 is bonded face-down onto the interposer substrate 120 using a high-precision flip-chip thermocompression bonder. The bonder provides placement accuracy of ±1.0 µm or better, which is verified by vision alignment using fiducial marks on both the PIC die and the interposer substrate. The bonding process parameters depend on the solder type:
(a) For Sn-Ag (SAC305) solder: bonding temperature 250–280°C, bonding force 5–50 N (depending on total bump count), bonding time 5–15 seconds.
(b) For In-based solder: bonding temperature 150–180°C, bonding force 3–30 N, bonding time 5–15 seconds.
During the bonding process, the solder caps on the PIC die bumps ar