RESPONSE TO COMMUNICATION UNDER RULES 161(1) AND 162 EPC

RESPONSE TO COMMUNICATION UNDER RULES 161(1) AND 162 EPC
European Patent Application No. EP 23 765 901.7
Derived from International Application No. PCT/US2023/010612
APPLICANT
Optiwave Semiconductor Corp. 4710 Ridgeview Parkway, Suite 300 Santa Clara, CA 95054 United States of America
TITLE OF INVENTION
Packaging and Thermal Management for Multi-Channel Silicon-Photonic Mach-Zehnder Modulator Assemblies
I. INTRODUCTORY LETTER / TRANSMITTAL
September 1, 2023
To: European Patent Office Receiving Section 80298 Munich Germany
From: Breitenfeld & Vogt Patentanwälte PartGmbB Leopoldstrasse 44 80802 Munich, Germany
1.1 Reference Information
Dear Sir or Madam,
1.2 Identification of Filing
This response is filed on behalf of the applicant, Optiwave Semiconductor Corp., a corporation organized and existing under the laws of the State of Delaware, United States of America, with its principal place of business at 4710 Ridgeview Parkway, Suite 300, Santa Clara, California 95054, United States of America. The response is filed through its duly appointed European professional representative, Breitenfeld & Vogt Patentanwälte PartGmbB, located at Leopoldstrasse 44, 80802 Munich, Germany.
This response is submitted within the prescribed time limit under Rule 161(1) and Rule 162 EPC, which provides for a period of six months from the deemed date of notification of the Rule 161/162 communication. The EPO communication was issued on July 12, 2023, with a deemed notification date of July 22, 2023, establishing a response deadline of January 22, 2024. The present response is therefore timely filed.
The instructions for the preparation and filing of this response were received from Peter Vassiliev (USPTO Registration No. 79,514) of Calderwood & Harkness LLP, 555 California Street, 42nd Floor, San Francisco, California 94104, United States of America, outside patent counsel to the applicant. Calderwood & Harkness LLP acts as lead prosecution counsel for the applicant's global patent portfolio, and Breitenfeld & Vogt Patentanwälte PartGmbB acts as the applicant's European professional representative in connection with all European patent applications in the Optiwave prosecution docket.
1.3 Summary of Actions Taken in This Response
In response to the communication under Rules 161(1) and 162 EPC, the applicant hereby takes the following actions:
1.  Amendments to the claims as permitted under Rule 161(2) EPC. The applicant submits a set of amended claims, narrowing the scope of the independent claims to more precisely define the packaging architecture and thermal management features of the claimed silicon-photonic Mach-Zehnder modulator assemblies, thereby further distinguishing the claimed invention over the prior art cited in the International Search Report and Written Opinion.
2.  Amendments to the description to conform the description to the requirements of the European Patent Convention. These amendments include the incorporation of references to the prior art cited in the International Search Report and Written Opinion in the introductory portion of the description, as required by Rule 42(1)(b) EPC, as well as conforming amendments to align the description with the amended claim scope.
3.  Voluntary submission of amended claims addressing matters raised in the International Search Report and Written Opinion (Chapter I report issued August 2, 2023) for PCT/US2023/010612 (designated as Application A5 in the applicant's prosecution docket). The applicant addresses the examiner's findings regarding novelty and inventive step, and presents supporting remarks in Section VI below.
4.  No observations under Rule 161(1) EPC are submitted at this time. The applicant elects to amend the application in the manner described herein, and respectfully reserves the right to submit further observations and arguments upon receipt of the Extended European Search Report.
The amended claims are submitted in clean copy format as Appendix A and in marked-up format (showing additions by underlining and deletions by strikethrough) as Appendix B. Amended description pages are submitted in clean and marked-up format as Appendix C. A copy of the International Search Report and Written Opinion for reference purposes is attached as Appendix D.
The applicant respectfully requests that the Examining Division take account of the amendments and remarks submitted herein in the further prosecution of this application.
Respectfully submitted,
Breitenfeld & Vogt Patentanwälte PartGmbB
II. PROCEDURAL BACKGROUND
2.1 International Application History
The present European patent application EP 23 765 901.7 derives from International Application No. PCT/US2023/010612, designated in the applicant's prosecution docket as Application A5. The international application was filed on January 9, 2023, at the United States Receiving Office (USPTO/RO) under the Patent Cooperation Treaty.
The international application claims priority from U.S. Provisional Application No. 63/297,841, filed January 10, 2022, establishing a priority date of January 10, 2022. The provisional application is entitled "Packaging and Thermal Management for Multi-Channel Silicon-Photonic Mach-Zehnder Modulator Assemblies" and was originally filed by the law firm of Kessler & Morin LLP (1750 Tysons Boulevard, Suite 800, McLean, Virginia 22102), which at that time served as outside patent counsel to Optiwave Semiconductor Corp. The engagement for patent prosecution services was subsequently transitioned from Kessler & Morin LLP to Calderwood & Harkness LLP effective February 14, 2022, and the present matter was assigned C&H Matter No. 1014-00005. All prosecution activities relating to Application A5 and its derivative national- and regional-phase applications have been conducted under the direction of Calderwood & Harkness LLP since that date.
U.S. Provisional Application No. 63/297,841 expired on January 10, 2023, upon the conclusion of its twelve-month statutory term under 35 U.S.C. § 119(e). Priority was preserved through the timely filing of both the PCT international application (PCT/US2023/010612, filed January 9, 2023) and the corresponding U.S. non-provisional application (discussed below), each of which was filed before the expiration of the twelve-month priority period.
The International Search Report and Written Opinion (Chapter I) for PCT/US2023/010612 was issued on August 2, 2023, by the United States Patent and Trademark Office (USPTO) acting as the International Searching Authority (ISA/US). The findings of the International Search Report and Written Opinion are summarized in Section III below and addressed in the remarks presented in Section VI.
2.2 European Regional Phase Entry
European patent application EP 23 765 901.7 was entered into the European regional phase on July 8, 2023. The European regional-phase entry was effected through the filing of the appropriate documents and payment of the required fees by Breitenfeld & Vogt Patentanwälte PartGmbB, acting as the duly appointed European professional representative for Optiwave Semiconductor Corp.
This application is designated as part of Sub-Family C of the Optiwave patent prosecution docket. Sub-Family C encompasses innovations directed to packaging and thermal management solutions for silicon-photonic modulator assemblies, and is distinct from Sub-Family A (covering the core Mach-Zehnder modulator electrode architecture) and Sub-Family B (covering electrode fabrication process innovations). The classification of prosecution families reflects the distinct technological contributions and claim scope of each application group, which address different aspects of the applicant's integrated silicon-photonic modulator platform technology.
2.3 Related Applications
For the convenience of the Examining Division, the applicant provides the following overview of related applications in the prosecution docket:
Companion European Application (Sub-Family B):
A companion European patent application, EP 23 741 682.3 (designated as Application B3 in the docket, Sub-Family B — Electrode Fabrication Process), was entered into the European regional phase on July 5, 2023. Application B3 derives from International Application No. PCT/US2023/010584 (designated as Application A4). While both EP 23 765 901.7 (the present application) and EP 23 741 682.3 relate to the applicant's silicon-photonic Mach-Zehnder modulator technology platform, they address distinct inventive aspects: the present application (Sub-Family C) is directed to packaging architecture and thermal management solutions, whereas EP 23 741 682.3 (Sub-Family B) is directed to electrode fabrication processes.
U.S. Non-Provisional Counterpart (Sub-Family C):
The U.S. non-provisional counterpart to the present application is U.S. Application No. 18/102,776 (designated as Application C1), filed January 29, 2024, at the United States Patent and Trademark Office. Application C1 is a national-stage entry under 35 U.S.C. § 371 of PCT/US2023/010612, claiming the same priority to U.S. Provisional Application No. 63/297,841.
Japanese National-Phase Counterpart (Sub-Family C):
The Japanese national-phase counterpart is JP 2024-542305 (designated as Application C3), entered into the Japanese national phase on July 8, 2023, through Nakashima & Togawa Patent Professional Corporation, Tokyo, Japan.
2.4 The Rule 161/162 Communication
Following the entry of the present application into the European regional phase, the European Patent Office issued a communication under Rules 161(1) and 162 EPC dated July 12, 2023 (deemed notification date: July 22, 2023). The communication invited the applicant to file amendments and/or observations in response to the International Search Report and Written Opinion issued for the international application from which the present European application derives.
Pursuant to the invitation set forth in the Rule 161/162 communication, the applicant hereby elects to file amended claims and corresponding description amendments, together with supporting remarks, as set forth in detail in Sections IV through VI below. The applicant does not submit standalone observations under Rule 161(1) at this time, but instead addresses the findings of the Written Opinion through the combination of claim amendments and remarks presented herein.
III. SUMMARY OF THE INTERNATIONAL SEARCH REPORT AND WRITTEN OPINION FINDINGS
3.1 Cited Prior Art References
The International Search Report issued on August 2, 2023, by the USPTO as International Searching Authority (ISA/US) for PCT/US2023/010612 cited the following prior art references:
Pinnacle Optics, Inc. is a Delaware corporation headquartered at 7200 Gateway Boulevard, Newark, California 94560, and is recognized as a principal competitor of the applicant in the silicon-photonic Mach-Zehnder modulator space. U.S. Patent Nos. 10,823,417 (D1) and 11,105,662 (D2) represent the primary blocking patents in this technology area and have been cited in the "X" category (relevant to novelty) and "Y" category (relevant to inventive step in combination) against various claims of the present application.
3.2 Novelty and Inventive Step Observations
The Written Opinion accompanying the International Search Report set forth the following principal findings regarding the patentability of the originally filed claims:
Novelty (Article 54 EPC / Article 33(2) PCT):
The Written Opinion indicated that independent claim 1 (directed to a multi-channel silicon-photonic Mach-Zehnder modulator assembly comprising a packaging architecture with integrated thermal management features) was found to lack novelty over D2 (U.S. Patent No. 11,105,662, Pinnacle Optics). Specifically, the examiner concluded that D2 disclosed a thermal interface material arrangement and heat sink configuration for an integrated photonic transceiver module that anticipated the broad language of original claim 1, including the recitation of a semiconductor substrate carrying a plurality of Mach-Zehnder modulator channels, a thermally conductive submount, and a lid structure providing a thermal path from the photonic integrated circuit to an external heat dissipation element.
Dependent claims 2 through 5, which further specified characteristics of the submount material (e.g., aluminum nitride with specified thermal conductivity ranges) and the thermal interface material (e.g., indium-based solder preforms), were also found to lack novelty over D2.
Independent claim 9 (directed to a method of assembling a thermally managed silicon-photonic Mach-Zehnder modulator package) was found to lack novelty over D2 in combination with the teachings of D1 (U.S. Patent No. 10,823,417, Pinnacle Optics), insofar as D1 disclosed process steps relating to the integration of segmented traveling-wave electrodes into a packaged modulator assembly.
Inventive Step (Article 56 EPC / Article 33(3) PCT):
The Written Opinion further indicated that, to the extent that certain claims were not found to lack novelty per se, several dependent claims (specifically claims 6 through 8 and claims 13 through 15) were found to lack an inventive step when considered in light of the combination of D1 and D2 (Y-category citations), and optionally in further view of D4 (WO 2021/178329 A1, NexGen Photonics Ltd.). The examiner reasoned that the combination of D1's modulator packaging disclosures with D2's thermal management teachings rendered the additional features of the dependent claims obvious to a person skilled in the art.
In particular, the examiner found that the feature of claim 6 (reciting a multi-zone thermal interface arrangement with differentiated thermal conductivity paths for the modulator channels and the driver electronics regions) was considered an obvious design choice in view of D2's general disclosure of thermal interface materials, combined with the well-known practice described in D3 (Zhang et al., IEEE JLT 2022) of providing zone-specific thermal management in co-packaged optical modules.
Clarity (Article 84 EPC):
The Written Opinion raised a clarity objection under Article 84 EPC with respect to claims 7 and 14, noting that the term "substantially thermally isolated" as used in these claims was considered insufficiently precise in the absence of a quantitative threshold or clear definition in the description. The examiner requested that the applicant either provide a quantitative definition or amend the claims to use more definite language.
Sufficiency of Disclosure (Article 83 EPC):
No objections regarding sufficiency of disclosure under Article 83 EPC were raised in the Written Opinion.
3.3 Unity of Invention Observations
The Written Opinion identified two groups of claims for purposes of the unity of invention analysis:
•  Group I (Claims 1–8): Directed to a multi-channel silicon-photonic Mach-Zehnder modulator assembly with an integrated thermal management packaging architecture (apparatus/device claims).
•  Group II (Claims 9–15): Directed to a method of assembling a thermally managed silicon-photonic Mach-Zehnder modulator package (method claims).
The examiner concluded that Groups I and II share a special technical feature (the multi-zone thermal interface arrangement applied to a silicon-photonic Mach-Zehnder modulator assembly), but noted that this special technical feature was found not to make a contribution over D2 in view of the novelty objection. Accordingly, a prima facie objection as to unity of invention was raised under Rule 13.1 and 13.2 PCT.
Notwithstanding the unity of invention objection, the International Searching Authority searched all claims of both groups, and the Written Opinion addressed the patentability of all fifteen originally filed claims. The applicant notes that the amended claims submitted herein maintain the two-group structure but introduce distinguishing features that the applicant submits constitute a special technical feature making a contribution over the cited prior art, thereby restoring unity of invention.
IV. AMENDED CLAIMS
4.1 Basis for Amendments
The claim amendments set forth herein are made under Rule 161(2) EPC, which permits the applicant to amend the application of its own volition upon entry into the European regional phase in response to the Rule 161/162 communication. The amendments are also consistent with the amendment opportunities available under Article 19 PCT and Rule 137(2) EPC.
All amendments find full support in the application as originally filed (International Application No. PCT/US2023/010612, filed January 9, 2023) and in the priority document (U.S. Provisional Application No. 63/297,841, filed January 10, 2022). Specifically, the features added to the amended claims are drawn from the following passages of the description as originally filed:
•  The multi-zone thermal interface arrangement with independently specified thermal conductivity zones: paragraphs [0034]–[0041] of the description as filed; Figures 3A–3C.
•  The thermally conductive submount comprising a coefficient of thermal expansion (CTE)-matched aluminum nitride substrate with a specified thermal conductivity of at least 170 W/m·K: paragraphs [0042]–[0047]; Table 1; Figure 4.
•  The compliant thermal interface layer interposed between the photonic integrated circuit die and the submount, the compliant layer comprising a patterned indium-tin alloy solder preform with a plurality of through-apertures aligned with optical waveguide regions: paragraphs [0048]–[0055]; Figure 5A.
•  The lid structure comprising a copper-tungsten alloy with a nickel-gold surface finish and a plurality of internal thermal vias providing a thermal conductivity path from an upper surface of the submount to an external heat sink mounting surface: paragraphs [0056]–[0063]; Figures 6A–6B.
•  The method steps of aligning, bonding, and thermally coupling the compliant thermal interface layer using a temperature-profiled reflow process at a peak temperature not exceeding 200°C: paragraphs [0071]–[0078]; Figure 8.
No new matter has been introduced by the amendments. All amended features are directly and unambiguously derivable from the application as originally filed, in full compliance with Article 123(2) EPC.
4.2 Summary of Claim Amendments
The following summarizes the principal amendments made to the claims:
Independent Claim 1 (Apparatus/Device Claim):
Independent claim 1 has been amended to more precisely define the packaging architecture and thermal management features of the claimed multi-channel silicon-photonic Mach-Zehnder modulator assembly. In particular, the amended claim specifies:
(a) that the thermally conductive submount comprises a CTE-matched aluminum nitride substrate having a thermal conductivity of at least 170 W/m·K;
(b) that the compliant thermal interface layer comprises a patterned indium-tin alloy solder preform including a plurality of through-apertures aligned with optical waveguide regions of the photonic integrated circuit, wherein the through-apertures are dimensioned to avoid direct thermal loading on the optical waveguide regions;
(c) that the lid structure comprises a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid to an external heat sink mounting surface, the thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure; and
(d) that the multi-zone thermal interface arrangement comprises at least a first thermal zone associated with the Mach-Zehnder modulator channels and a second thermal zone associated with the driver electronics region, the first and second thermal zones having independently specified thermal resistance values.
These features collectively define the packaging and thermal management architecture that is the focus of the Sub-Family C innovations and that the applicant submits is not disclosed or suggested by any of the cited prior art references, individually or in combination.
Independent Claim 9 (Method Claim):
Independent claim 9 has been amended to specify the method steps for thermal management integration, including:
(a) providing a CTE-matched aluminum nitride submount;
(b) forming the patterned indium-tin alloy solder preform with through-apertures aligned to the optical waveguide regions;
(c) aligning and bonding the photonic integrated circuit die to the submount through the patterned solder preform using a temperature-profiled reflow process at a peak temperature not exceeding 200°C; and
(d) attaching the copper-tungsten lid structure with internal thermal vias to the submount assembly, thereby establishing a continuous thermal path from the photonic integrated circuit to the external heat sink mounting surface.
Dependent Claims:
Dependent claims 2 through 8 (dependent on independent claim 1) and dependent claims 10 through 15 (dependent on independent claim 9) have been amended for consistency with the amended independent claims. Certain dependent claims have been renumbered to account for the consolidation of original claims 4 and 5 into a single dependent claim (now amended claim 4), and original claims 13 and 14 into a single dependent claim (now amended claim 12).
Claim Count:
The original application as filed contained fifteen (15) claims (claims 1–15). The amended claim set contains thirteen (13) claims (claims 1–13), reflecting the consolidation noted above.
Claim Categories:
The amended claims include apparatus/device claims (claims 1–7) and method claims (claims 8–13).
Sub-Family C Focus:
The applicant emphasizes that the claims as amended are directed exclusively to packaging and thermal management innovations for silicon-photonic Mach-Zehnder modulator assemblies. The amended claims do not recite features relating to the modulator electrode architecture itself (which is the subject of Sub-Family A) or the electrode fabrication process (which is the subject of Sub-Family B, prosecuted in companion European application EP 23 741 682.3). This clear delineation of claim scope across the prosecution sub-families avoids potential double-patenting or overlap issues.
4.3 Clean Copy of Amended Claims
A clean copy of the complete set of amended claims (claims 1–13) is presented in Appendix A hereto, formatted in accordance with EPO requirements. The claims are numbered sequentially and designate the appropriate claim category (apparatus or method).
4.4 Marked-Up Copy of Amended Claims
A marked-up copy of the complete set of amended claims, showing all amendments relative to the claims as originally filed in PCT/US2023/010612, is presented in Appendix B hereto. In accordance with EPO practice, additions are indicated by underlining and deletions are indicated by strikethrough text.
V. AMENDMENTS TO THE DESCRIPTION
5.1 Adaptation of Description to EPC Requirements
The applicant has made the following conforming amendments to the description to satisfy the formal requirements of the European Patent Convention:
Terminology Adaptations:
References to United States-specific patent terminology have been converted to EPC-compliant language where appropriate. For example, references to "claims" as "the appended claims" have been updated to "the claims" in conformity with EPO drafting practice. References to "the specification" have been replaced with "the description" where such references refer to the descriptive portion of the application. References to "embodiments of the present invention" have been replaced with "embodiments" or "exemplary embodiments" to avoid the implication that the claims are limited to the specifically described embodiments, consistent with EPO Guidelines for Examination, Part F-IV, 4.5.
Citation of Prior Art (Rule 42(1)(b) EPC):
The introductory portion of the description has been amended to include references to the prior art cited in the International Search Report and Written Opinion, as required by Rule 42(1)(b) EPC. Specifically, the following references have been acknowledged in the amended description:
•  U.S. Patent No. 10,823,417 (D1, Pinnacle Optics, Inc.) is acknowledged as representative of the general state of the art in segmented traveling-wave electrode designs for silicon-photonic Mach-Zehnder modulators. The description identifies the general teachings of D1 regarding electrode segmentation and velocity matching in high-speed modulator designs, while noting that D1 does not address the specific packaging and thermal management challenges that are the focus of the present invention.
•  U.S. Patent No. 11,105,662 (D2, Pinnacle Optics, Inc.) is acknowledged as disclosing thermal interface materials and heat sink configurations for integrated photonic transceiver modules. The description identifies the general teachings of D2 regarding the use of thermal interface materials in photonic module packaging, while noting that D2 does not disclose the specific multi-zone thermal interface arrangement with patterned solder preforms including through-apertures aligned with optical waveguide regions, as recited in the amended claims of the present application.
•  WO 2021/178329 A1 (D4, NexGen Photonics Ltd.) is acknowledged as disclosing a multi-channel photonic module with integrated thermal regulation, while noting that D4 does not disclose the specific combination of CTE-matched aluminum nitride submount, patterned indium-tin alloy solder preform, and copper-tungsten lid structure with internal thermal vias, as recited in the amended claims.
The references to D3 (Zhang et al., IEEE JLT 2022) and D5 (U.S. Patent Application Publication No. 2022/0057612 A1, Luminos Technologies, Inc.) have been acknowledged in a general manner as background publications illustrating the state of the art in thermal management for co-packaged optical modules.
5.2 Consistency with Amended Claims
Minor conforming amendments have been made to ensure that the description supports the scope of the amended claims. These amendments are limited to ensuring consistency between the terminology used in the amended claims and the corresponding passages of the description, and do not introduce any substantive new matter. In particular:
•  Paragraph [0036] has been amended to clarify that the "multi-zone thermal interface arrangement" described therein corresponds to the feature recited in amended claim 1, with the first thermal zone associated with the Mach-Zehnder modulator channels and the second thermal zone associated with the driver electronics region.
•  Paragraph [0049] has been amended to specify that the "through-apertures" in the patterned solder preform are "dimensioned to avoid direct thermal loading on the optical waveguide regions," consistent with the language of amended claim 1(b).
•  Paragraph [0058] has been amended to clarify that the thermal conductivity of the internal thermal vias in the lid structure is "at least 250 W/m·K," consistent with the language of amended claim 1(c).
No substantive new matter has been added to the description.
5.3 Clean and Marked-Up Pages
The following description pages have been amended and are submitted as replacement pages:
Replacement pages are provided in both clean copy and marked-up copy format in Appendix C hereto. In the marked-up copies, additions are indicated by underlining and deletions are indicated by strikethrough text.
VI. REMARKS IN SUPPORT OF AMENDMENTS
6.1 Response to Novelty Objections
The applicant respectfully submits that the amended claims are novel over each of the cited prior art references, considered individually, and addresses the specific novelty objections raised in the Written Opinion as follows.
Distinguishing Amended Claim 1 Over D2 (U.S. Patent No. 11,105,662, Pinnacle Optics):
The Written Opinion found original claim 1 to lack novelty over D2. The applicant acknowledges that D2 discloses, in general terms, the use of thermal interface materials and heat sink configurations in photonic transceiver module packaging. However, the applicant respectfully submits that D2 does not disclose, either explicitly or implicitly, the following combination of features now recited in amended claim 1:
(i) A compliant thermal interface layer comprising a patterned indium-tin alloy solder preform including a plurality of through-apertures aligned with optical waveguide regions of the photonic integrated circuit, wherein the through-apertures are dimensioned to avoid direct thermal loading on the optical waveguide regions.
D2 discloses the use of thermal interface materials (specifically, thermal greases and pad-type materials) applied uniformly across the interface between the photonic integrated circuit and the submount. D2 does not disclose or suggest the concept of patterning the thermal interface layer with through-apertures that are specifically aligned with the optical waveguide regions to avoid thermal loading on those regions. This feature is a key innovation of the present invention, as it addresses the problem of thermally induced phase errors in the Mach-Zehnder interferometer arms caused by non-uniform thermal loading from the die-attach interface — a problem that is not recognized in D2.
(ii) A lid structure comprising a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid to an external heat sink mounting surface, the thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure.
D2 discloses a copper lid with external fins for convective cooling. D2 does not disclose the use of a copper-tungsten alloy lid body, a nickel-gold surface finish, or internal thermal vias within the lid structure providing a specified minimum thermal conductivity. The copper-tungsten alloy selection is critical to achieving CTE matching with the aluminum nitride submount, while the internal thermal vias provide a high-conductivity path that is superior to the uniform-body copper lid disclosed in D2.
(iii) A multi-zone thermal interface arrangement comprising at least a first thermal zone associated with the Mach-Zehnder modulator channels and a second thermal zone associated with the driver electronics region, the first and second thermal zones having independently specified thermal resistance values.
D2 does not disclose a multi-zone thermal interface arrangement with independently specified thermal resistance values for different functional regions of the module. D2's thermal management approach is undifferentiated across the module footprint, treating the modulator channels and the driver electronics as a single thermal domain. The present invention recognizes that the thermal management requirements for the modulator channels (which are sensitive to thermally induced phase errors) differ fundamentally from those for the driver electronics (which generate significantly higher heat flux densities), and provides independently optimized thermal paths for each zone.
Accordingly, the applicant submits that amended claim 1, which requires the combination of all of the above features, is novel over D2.
Distinguishing Amended Claim 1 Over D1 (U.S. Patent No. 10,823,417, Pinnacle Optics):
D1 is directed to the design of segmented traveling-wave electrodes for silicon-photonic Mach-Zehnder modulators and is primarily concerned with the electrical characteristics of the electrode architecture (impedance matching, velocity matching, RF loss minimization). D1 does not address packaging or thermal management in any meaningful detail. While D1 includes a brief description of a generic hermetic package enclosing the modulator chip (see D1, column 12, lines 45–62), this description does not include any of the specific thermal management features recited in amended claim 1. The applicant therefore submits that amended claim 1 is clearly novel over D1.
Distinguishing Amended Claim 8 (Method Claim) Over D2 and D1:
Amended independent claim 8 (originally claim 9) is directed to a method of assembling a thermally managed silicon-photonic Mach-Zehnder modulator package. The Written Opinion found the original method claim to lack novelty over D2 in combination with D1. The applicant respectfully submits that, even if D2 and D1 were to be combined (which combination is itself not self-evident), neither reference discloses the specific method steps now recited in amended claim 8, including:
•  Forming the patterned indium-tin alloy solder preform with through-apertures aligned to the optical waveguide regions (not disclosed in either D1 or D2);
•  Aligning and bonding the photonic integrated circuit die to the submount through the patterned solder preform using a temperature-profiled reflow process at a peak temperature not exceeding 200°C (D2 discloses conventional solder reflow at 260°C; the present invention's low-temperature reflow profile is specifically designed to avoid thermally induced stress damage to the photonic waveguide structures); and
•  Attaching the copper-tungsten lid structure with internal thermal vias to the submount assembly (not disclosed in either D1 or D2).
Accordingly, the applicant submits that amended claim 8 is novel over the cited prior art.
6.2 Response to Inventive Step Objections
The applicant further submits that the amended claims involve an inventive step within the meaning of Article 56 EPC. The applicant presents the following analysis under the problem-solution approach employed by the European Patent Office, in accordance with the EPO Guidelines for Examination, Part G-VII, 5.
Identification of the Closest Prior Art:
The applicant accepts that D2 (U.S. Patent No. 11,105,662, Pinnacle Optics) constitutes the closest prior art for purposes of the inventive step analysis, as D2 is directed to the same general technical field (thermal management for packaged photonic transceiver modules) and shares the greatest number of features with the claimed invention.
Determination of Distinguishing Features:
As set forth in Section 6.1 above, amended claim 1 differs from D2 in at least the following respects:
(a) The patterned indium-tin alloy solder preform with through-apertures aligned with and dimensioned to avoid thermal loading on the optical waveguide regions;
(b) The copper-tungsten alloy lid body with nickel-gold surface finish and internal thermal vias providing at least 250 W/m·K thermal conductivity; and
(c) The multi-zone thermal interface arrangement with independently specified thermal resistance values for the modulator channel zone and the driver electronics zone.
Formulation of the Objective Technical Problem:
In view of the distinguishing features identified above, the objective technical problem solved by the present invention, starting from D2, can be formulated as:
How to provide a packaging and thermal management architecture for a multi-channel silicon-photonic Mach-Zehnder modulator assembly that (i) minimizes thermally induced phase errors in the modulator channels by avoiding direct thermal loading on the optical waveguide regions from the die-attach interface, (ii) provides CTE-matched structural elements to minimize thermo-mechanical stress, and (iii) provides independently optimized thermal dissipation paths for the modulator channels and the driver electronics, thereby enabling reliable operation at data rates of 800 Gbit/s and beyond in high-density data-center optical transceiver modules.
Non-Obviousness of the Claimed Solution:
The applicant submits that the claimed solution to the above objective technical problem would not have been obvious to a person skilled in the art at the priority date, for the following reasons:
First, the concept of patterning the thermal interface solder preform with through-apertures specifically aligned with the optical waveguide regions is not disclosed or suggested by any of the cited references. D2 teaches the uniform application of thermal interface materials and does not recognize the problem of thermally induced phase errors arising from the die-attach interface. The Zhang et al. publication (D3) discusses general thermal management challenges in co-packaged optics but does not disclose or suggest the specific solution of patterning the solder preform with waveguide-aligned through-apertures. A person skilled in the art reading D2 and D3 would not have been motivated to introduce through-apertures in the solder preform, as this approach counterintuitively reduces the total contact area of the thermal interface (and thus potentially increases overall thermal resistance at the interface), in exchange for the benefit of eliminating localized thermal loading on the optically active regions. This trade-off is non-obvious and represents a departure from the prevailing approach in the art, which seeks to maximize thermal interface contact area.
Second, the selection of a copper-tungsten alloy for the lid body, combined with internal thermal vias, represents a non-obvious combination of material choices and structural features. D2 discloses a copper lid without thermal vias, which provides high thermal conductivity but poor CTE matching with the aluminum nitride submount (CTE of copper: approximately 17 ppm/°C; CTE of aluminum nitride: approximately 4.5 ppm/°C). The copper-tungsten alloy used in the present invention has a CTE of approximately 6.5–7.0 ppm/°C, providing significantly improved CTE matching with the submount. However, copper-tungsten has a lower intrinsic thermal conductivity than pure copper, which would ordinarily be seen as a disadvantage in thermal management applications. The present invention overcomes this trade-off through the use of internal thermal vias within the lid structure, which provide localized high-conductivity paths (at least 250 W/m·K) through the lid body. This combination of CTE-matched lid material with internal thermal vias is not disclosed or suggested by any of the cited references.
Third, the multi-zone thermal interface arrangement with independently specified thermal resistance values for the modulator channels and the driver electronics is not disclosed or suggested by any of the cited references. While D3 (Zhang et al.) generally discusses the different thermal management requirements of different components within a co-packaged optical module, D3 does not disclose or suggest the specific implementation of independently specified thermal resistance values achieved through a multi-zone arrangement. D4 (WO 2021/178329 A1) discloses a multi-channel photonic module with integrated thermal regulation, but achieves thermal regulation through active thermoelectric cooling elements rather than through a passive multi-zone thermal interface arrangement with independently specified thermal resistance values. A person skilled in the art would not have been motivated to combine the teachings of D2 and D4, as they employ fundamentally different thermal management strategies (passive versus active thermal regulation).
Technical Effect:
The packaging and thermal management features recited in the amended claims achieve the following technical effects, which are demonstrated in the application as filed:
•  Reduction of thermally induced phase errors in the Mach-Zehnder modulator channels by at least 40% compared to conventional uniform thermal interface approaches (see paragraphs [0064]–[0067] and Figure 7A of the application as filed);
•  Reduction of thermo-mechanical stress at the die-attach interface by approximately 35% due to CTE matching between the copper-tungsten lid, the aluminum nitride submount, and the silicon photonic integrated circuit die (see paragraphs [0060]–[0062] and Table 2 of the application as filed);
•  Reliable operation at ambient temperatures up to 85°C in 800G QSFP-DD and 1.6T OSFP module form factors, with a measured junction-to-case thermal resistance of less than 0.8°C/W for the modulator channels and less than 0.5°C/W for the driver electronics (see paragraphs [0079]–[0082] and Figure 9 of the application as filed).
These technical effects are significant for the deployment of silicon-photonic Mach-Zehnder modulators in high-density data-center optical transceiver modules operating at 800 Gbit/s and 1.6 Tbit/s data rates, where thermal management is a critical limiting factor for module performance, reliability, and lifetime.
Accordingly, the applicant respectfully submits that the amended claims involve an inventive step over the cited prior art.
6.3 Response to Clarity / Formal Objections
The Written Opinion raised a clarity objection under Article 84 EPC with respect to original claims 7 and 14, which used the term "substantially thermally isolated" without providing a quantitative threshold or clear definition.
In response, the applicant has amended the relevant dependent claims (now amended claims 6 and 12) to replace the term "substantially thermally isolated" with the more precise formulation "thermally isolated by a thermal resistance of at least 15°C·cm²/W," which provides a clear, quantitative threshold. This threshold is supported by the description as originally filed (see paragraph [0038], which states: "The thermal isolation between the first and second thermal zones is characterized by a thermal resistance of at least 15°C·cm²/W, which is sufficient to prevent significant thermal crosstalk between the modulator channels and the driver electronics during steady-state operation."). The applicant submits that this amendment fully addresses the clarity objection.
The applicant further confirms that the amended claims comply with the claim drafting requirements of Rule 43 EPC, including the requirements for claim structure (independent claims followed by dependent claims), claim referencing (each dependent claim referring to at least one preceding claim), and claim conciseness.
6.4 Request for Further Processing
The applicant respectfully requests that the Examining Division proceed with substantive examination of the present application in light of the amendments and remarks submitted herein.
The applicant notes that, as of the date of this response, the Extended European Search Report (EESR) has not yet been issued for this application (EP 23 765 901.7). The applicant understands that the EESR will be prepared by the EPO Search Division in due course and anticipates receiving the EESR at a future date. Upon receipt of the EESR, the applicant will have the opportunity to file further observations and amendments in response to the search and examination opinions set forth therein, and the applicant respectfully reserves the right to do so.
The applicant further respectfully requests that the Examining Division take into account the amended claims and description pages submitted herewith when preparing the Extended European Search Report and the communication under Article 94(3) EPC, to the extent that this is procedurally feasible.
VII. FORMAL MATTERS
7.1 Power of Attorney / Authorization
Breitenfeld & Vogt Patentanwälte PartGmbB is authorized to act as European professional representative for Optiwave Semiconductor Corp. before the European Patent Office pursuant to a general authorization filed with the EPO on July 8, 2023, upon entry of the present application into the European regional phase. A copy of the general authorization (Form EPO 1003) is on file with the EPO under reference BV-2023-EU-0482. No additional individual power of attorney is required for the filing of this response.
7.2 Designation of Inventor
The applicant confirms that the designations of inventor were properly filed upon entry of the present application into the European regional phase on July 8, 2023, in compliance with Rule 19 EPC. The following individuals are designated as inventors of the subject matter of the present application:
1.  Dr. Rajan Menon, residing at 2817 Greenmont Lane, Los Altos, California 94024, United States of America
2.  Dr. Lena Strickland, residing at 14 Thornberry Circle, Sunnyvale, California 94086, United States of America
3.  Dr. Feng-Yi Chen, residing at 951 Rosewood Drive, Palo Alto, California 94303, United States of America
4.  Dr. Arjun Dasgupta, residing at 408 Bayshore Road, Apt. 12B, Mountain View, California 94043, United States of America
Each of the named inventors has executed a declaration of inventorship and waiver of right to be mentioned as inventor (to the extent applicable) in connection with the filing of the international application. The applicant is the sole assignee of the entire right, title, and interest in and to the invention, by virtue of employment agreements and invention assignment agreements executed by each of the named inventors.
7.3 Applicant Information
All communications from the European Patent Office in connection with this application should be directed to Breitenfeld & Vogt Patentanwälte PartGmbB at the address set forth above.
7.4 Fee Status
The applicant confirms that all required fees for European regional-phase entry have been duly paid as of the date of entry, July 8, 2023, including:
•  Filing fee under Rule 17(1) EPC;
•  Designation fee (all Contracting States designated);
•  Examination fee under Rule 17(2) EPC; and
•  Claims fees for claims in excess of fifteen under Rule 45(1) EPC (no additional claims fees are due at this time, as the amended claim set contains thirteen claims, which does not exceed the threshold of fifteen claims).
No additional fees are believed to be due in connection with the filing of this response. Should any additional fees be required, the applicant respectfully requests that the EPO debit the deposit account of Breitenfeld & Vogt Patentanwälte PartGmbB (Deposit Account No. 28-107924) in the amount of any such fees, and the applicant authorizes Breitenfeld & Vogt to make such payment on its behalf.
7.5 Signature.  
Breitenfeld & Vogt Patentanwälte PartGmbB
By: ________
Dr. Matthias Vogt European Patent Attorney Breitenfeld & Vogt Patentanwälte PartGmbB Leopoldstrasse 44 80802 Munich, Germany
Date: September 1, 2023
APPENDIX A — AMENDED CLAIMS (CLEAN COPY)
CLAIMS
Claims 1–7: Apparatus Claims
1. A multi-channel silicon-photonic Mach-Zehnder modulator assembly, comprising:
a silicon photonic integrated circuit die comprising a plurality of Mach-Zehnder modulator channels, each modulator channel comprising at least one optical waveguide region;
a thermally conductive submount comprising a coefficient-of-thermal-expansion-matched aluminum nitride substrate having a thermal conductivity of at least 170 W/m·K, the silicon photonic integrated circuit die being mounted on an upper surface of the submount;
a compliant thermal interface layer interposed between the silicon photonic integrated circuit die and the upper surface of the submount, the compliant thermal interface layer comprising a patterned indium-tin alloy solder preform including a plurality of through-apertures, each through-aperture being aligned with a respective optical waveguide region of the photonic integrated circuit and dimensioned to avoid direct thermal loading on the respective optical waveguide region;
a lid structure disposed over the silicon photonic integrated circuit die and attached to the submount, the lid structure comprising a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid structure to an external heat sink mounting surface, the internal thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure; and
a multi-zone thermal interface arrangement comprising at least a first thermal zone associated with the plurality of Mach-Zehnder modulator channels and a second thermal zone associated with a driver electronics region of the assembly, the first and second thermal zones having independently specified thermal resistance values.
2. The assembly of claim 1, wherein the aluminum nitride substrate has a coefficient of thermal expansion in the range of 4.0 to 5.5 ppm/°C, and the copper-tungsten alloy body of the lid structure has a coefficient of thermal expansion in the range of 6.0 to 7.5 ppm/°C.
3. The assembly of claim 1 or claim 2, wherein the patterned indium-tin alloy solder preform has a thickness in the range of 15 to 50 micrometers, and wherein each through-aperture has a lateral dimension that is at least 1.2 times a lateral dimension of the corresponding optical waveguide region.
4. The assembly of any one of claims 1 to 3, wherein the thermal resistance of the first thermal zone is in the range of 0.6 to 1.0°C/W, and the thermal resistance of the second thermal zone is in the range of 0.3 to 0.6°C/W.
5. The assembly of any one of claims 1 to 4, wherein the internal thermal vias of the lid structure comprise copper pillars embedded in the copper-tungsten alloy body, the copper pillars having a diameter in the range of 100 to 500 micrometers and arranged in an array aligned with the plurality of Mach-Zehnder modulator channels.
6. The assembly of any one of claims 1 to 5, wherein the first thermal zone and the second thermal zone are thermally isolated from each other by a thermal resistance of at least 15°C·cm²/W.
7. The assembly of any one of claims 1 to 6, further comprising an external heat sink attached to the heat sink mounting surface of the lid structure, the external heat sink providing a total thermal dissipation capacity of at least 15 watts at an ambient temperature of 85°C.
Claims 8–13: Method Claims
8. A method of assembling a thermally managed silicon-photonic Mach-Zehnder modulator package, the method comprising:
providing a thermally conductive submount comprising a coefficient-of-thermal-expansion-matched aluminum nitride substrate having a thermal conductivity of at least 170 W/m·K;
forming a patterned indium-tin alloy solder preform having a plurality of through-apertures, each through-aperture configured to be aligned with a respective optical waveguide region of a silicon photonic integrated circuit die comprising a plurality of Mach-Zehnder modulator channels;
disposing the patterned solder preform on an upper surface of the submount and aligning the silicon photonic integrated circuit die over the solder preform such that each through-aperture is aligned with the respective optical waveguide region;
bonding the silicon photonic integrated circuit die to the submount through the patterned solder preform using a temperature-profiled reflow process at a peak temperature not exceeding 200°C, thereby forming a compliant thermal interface layer between the die and the submount, the through-apertures being dimensioned to avoid direct thermal loading on the optical waveguide regions; and
attaching a lid structure to the submount, the lid structure comprising a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid structure to an external heat sink mounting surface, the internal thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure, thereby establishing a continuous thermal path from the silicon photonic integrated circuit die to the external heat sink mounting surface.
9. The method of claim 8, further comprising establishing a multi-zone thermal interface arrangement by configuring the patterned solder preform to provide a first thermal zone associated with the plurality of Mach-Zehnder modulator channels and a second thermal zone associated with a driver electronics region, the first and second thermal zones having independently specified thermal resistance values.
10. The method of claim 8 or claim 9, wherein the temperature-profiled reflow process comprises:
a preheat stage at a temperature in the range of 100 to 150°C for a duration of 30 to 90 seconds;
a ramp stage increasing the temperature from the preheat temperature to the peak temperature at a rate not exceeding 3°C per second; and
a peak stage at the peak temperature not exceeding 200°C for a duration of 10 to 30 seconds.
11. The method of any one of claims 8 to 10, wherein forming the patterned solder preform comprises:
providing a sheet of indium-tin alloy having a thickness in the range of 15 to 50 micrometers; and
forming the plurality of through-apertures by laser ablation or mechanical punching, each through-aperture having a lateral dimension that is at least 1.2 times a lateral dimension of the corresponding optical waveguide region.
12. The method of any one of claims 8 to 11, wherein establishing the multi-zone thermal interface arrangement further comprises thermally isolating the first thermal zone from the second thermal zone by a thermal resistance of at least 15°C·cm²/W.
13. The method of any one of claims 8 to 12, further comprising attaching an external heat sink to the heat sink mounting surface of the lid structure, the external heat sink providing a total thermal dissipation capacity of at least 15 watts at an ambient temperature of 85°C.
APPENDIX B — AMENDED CLAIMS (MARKED-UP COPY)
CLAIMS (Marked-Up Copy — Additions Underlined, Deletions Struck Through)
Claims 1–7: Apparatus Claims
1. A multi-channel silicon-photonic Mach-Zehnder modulator assembly, comprising:
a silicon photonic integrated circuit die comprising a plurality of Mach-Zehnder modulator channels, each modulator channel comprising at least one optical waveguide region;
a thermally conductive submount ~~comprising a thermally conductive substrate~~ comprising a coefficient-of-thermal-expansion-matched aluminum nitride substrate having a thermal conductivity of at least 170 W/m·K, the silicon photonic integrated circuit die being mounted on an upper surface of the submount;
a ~~thermal interface material~~ compliant thermal interface layer interposed between the silicon photonic integrated circuit die and the upper surface of the submount, the ~~thermal interface material providing a thermal path from the die to the submount~~ compliant thermal interface layer comprising a patterned indium-tin alloy solder preform including a plurality of through-apertures, each through-aperture being aligned with a respective optical waveguide region of the photonic integrated circuit and dimensioned to avoid direct thermal loading on the respective optical waveguide region;
a lid structure disposed over the silicon photonic integrated circuit die and attached to the submount, the lid structure ~~providing a thermal path from the die to an external heat dissipation element~~ comprising a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid structure to an external heat sink mounting surface, the internal thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure; and
a multi-zone thermal interface arrangement comprising at least a first thermal zone associated with the plurality of Mach-Zehnder modulator channels and a second thermal zone associated with a driver electronics region of the assembly, the first and second thermal zones having independently specified thermal resistance values.
2. The assembly of claim 1, wherein the aluminum nitride substrate has a coefficient of thermal expansion in the range of 4.0 to 5.5 ppm/°C, and ~~wherein the submount has a thermal conductivity of at least 170 W/m·K~~ the copper-tungsten alloy body of the lid structure has a coefficient of thermal expansion in the range of 6.0 to 7.5 ppm/°C.
3. The assembly of claim 1 or claim 2, wherein the ~~thermal interface material comprises an indium-based solder preform~~ patterned indium-tin alloy solder preform has a thickness in the range of 15 to 50 micrometers, and wherein each through-aperture has a lateral dimension that is at least 1.2 times a lateral dimension of the corresponding optical waveguide region.
4. The assembly of any one of claims 1 to 3, wherein ~~the indium-based solder preform has a specified thermal conductivity~~ the thermal resistance of the first thermal zone is in the range of 0.6 to 1.0°C/W, and the thermal resistance of the second thermal zone is in the range of 0.3 to 0.6°C/W.
~~5. The assembly of claim 4, wherein the indium-based solder preform has a thickness in the range of 15 to 50 micrometers.~~
5. The assembly of any one of claims 1 to 4, wherein the internal thermal vias of the lid structure comprise copper pillars embedded in the copper-tungsten alloy body, the copper pillars having a diameter in the range of 100 to 500 micrometers and arranged in an array aligned with the plurality of Mach-Zehnder modulator channels.
6. The assembly of any one of claims 1 to 5, wherein ~~the modulator channels are substantially thermally isolated from a driver electronics region~~ the first thermal zone and the second thermal zone are thermally isolated from each other by a thermal resistance of at least 15°C·cm²/W.
~~7. The assembly of claim 6, wherein a driver electronics region is substantially thermally isolated from the modulator channels.~~
7. The assembly of any one of claims 1 to 6, ~~wherein the lid structure comprises a metal lid with external cooling fins~~ further comprising an external heat sink attached to the heat sink mounting surface of the lid structure, the external heat sink providing a total thermal dissipation capacity of at least 15 watts at an ambient temperature of 85°C.
~~8. The assembly of claim 7, wherein the metal lid is a copper lid.~~
Claims 8–13: Method Claims
(Original claims 9–15 renumbered as claims 8–13; amendments shown correspondingly.)
8. A method of assembling a thermally managed silicon-photonic Mach-Zehnder modulator package, the method comprising:
providing a thermally conductive submount ~~comprising a thermally conductive substrate~~ comprising a coefficient-of-thermal-expansion-matched aluminum nitride substrate having a thermal conductivity of at least 170 W/m·K;
forming a patterned indium-tin alloy solder preform having a plurality of through-apertures, each through-aperture configured to be aligned with a respective optical waveguide region of a silicon photonic integrated circuit die comprising a plurality of Mach-Zehnder modulator channels;
~~applying a thermal interface material to the submount~~ disposing the patterned solder preform on an upper surface of the submount and aligning ~~a~~ the silicon photonic integrated circuit die over the ~~submount~~ solder preform such that each through-aperture is aligned with the respective optical waveguide region;
bonding the silicon photonic integrated circuit die to the submount ~~using a reflow process~~ through the patterned solder preform using a temperature-profiled reflow process at a peak temperature not exceeding 200°C, thereby forming a compliant thermal interface layer between the die and the submount, the through-apertures being dimensioned to avoid direct thermal loading on the optical waveguide regions; and
attaching a lid structure to the submount, the lid structure ~~providing a thermal path from the die to an external heat dissipation element~~ comprising a copper-tungsten alloy body with a nickel-gold surface finish and a plurality of internal thermal vias extending from an inner surface of the lid structure to an external heat sink mounting surface, the internal thermal vias providing a thermal conductivity of at least 250 W/m·K through the lid structure, thereby establishing a continuous thermal path from the silicon photonic integrated circuit die to the external heat sink mounting surface.
9. The method of claim 8, further comprising establishing a multi-zone thermal interface arrangement by configuring the patterned solder preform to provide a first thermal zone associated with the plurality of Mach-Zehnder modulator channels and a second thermal zone associated with a driver electronics region, the first and second thermal zones having independently specifie