PRIVILEGED AND CONFIDENTIAL — ATTORNEY WORK PRODUCT
CALDERWOOD & HARKNESS LLP intellectual Property Group
MEMORANDUM
CONFIDENTIALITY NOTICE: This memorandum is protected by the attorney-client privilege and the work product doctrine. It is prepared in anticipation of litigation and for the purpose of providing legal advice to Optiwave Semiconductor Corp. ("OWS" or the "Client"). This document contains mental impressions, conclusions, opinions, and legal theories of attorneys at Calderwood & Harkness LLP. It is not intended for disclosure to any third party and should not be distributed, copied, or otherwise disseminated without prior written authorization from Catherine Bloom. Any inadvertent disclosure does not constitute a waiver of any applicable privilege.
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1. Executive Summary
The purpose of this memorandum is to catalog, organize, and analyze the key prior art references identified through comprehensive patent and non-patent literature searches conducted in connection with the prosecution of Optiwave Semiconductor Corp.'s twelve-application patent family covering next-generation silicon-photonics modulator architecture and related fabrication processes, packaging, and thermal management structures. The searches were conducted across the United States Patent and Trademark Office (USPTO), the World intellectual Property Organization (WIPO), the European Patent Office (EPO), and the Japan Patent Office (JPO), as well as principal technical publication databases, between October 2022 and November 30, 2022.
All twelve applications in the OWS patent family trace their priority to U.S. Provisional Application No. 63/297,841, which was filed on January 10, 2022. The provisional application was originally prepared and filed by Kessler & Morin LLP under the direction of Dr. Helen Kessler before the engagement transitioned to Calderwood & Harkness LLP in mid-2022. The full application family is organized into three sub-families as described in detail in Section 4 below: Sub-Family A (Core Modulator Architecture, comprising five applications designated A1 through A5), Sub-Family B (Electrode Fabrication Process, comprising four applications designated B1 through B4), and Sub-Family C (Packaging & Thermal Management, comprising three applications designated C1 through C3).
The prior art landscape for OWS's technology is dominated by two issued United States patents held by Pinnacle Optics, Inc., a competitor headquartered in Newark, California. Specifically:
• U.S. Patent No. 10,823,417 (the "'417 patent"), issued November 3, 2020, entitled "Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode"; and
• U.S. Patent No. 11,105,662 (the "'662 patent"), issued August 31, 2021, entitled "Multi-Segment Electrode Structure for High-Bandwidth Silicon-Photonic Modulator."
Both Pinnacle patents claim silicon-photonic Mach-Zehnder modulator ("MZM") structures employing segmented traveling-wave electrodes ("TWEs") that overlap substantially with the technological space occupied by OWS's pending claims, particularly those in Sub-Family A. Pinnacle's patents were prosecuted by Cavanaugh Holt & Sayer LLP under the direction of Grant Sayer. A published continuation application in the Pinnacle family (Reference P-3, discussed in Section 3.1.3) adds further complexity, as its claims are directed to electrode fabrication processes that may bear on OWS's Sub-Family B claims.
Summary Finding: Based on our analysis, OWS's claims can be distinguished from the most material prior art through emphasis on the "tapered impedance-matching" electrode geometry feature and specific fabrication process steps that are absent from the Pinnacle patents and from all other identified references. This tapered impedance-matching feature — which involves a continuously varying impedance profile along the length of each electrode segment, achieved through a specific taper geometry on a silicon-on-insulator ("SOI") substrate — represents the principal point of novelty and non-obviousness for OWS's claims. However, careful claim drafting is essential. The risk of examiner rejections based on combinations of the Pinnacle patents with references disclosing impedance-grading or impedance-tapering concepts in non-silicon material systems (lithium niobate and III-V compound semiconductors) is moderate to high, and the prosecution team must be prepared to present robust arguments distinguishing OWS's silicon-photonic-specific approach from these non-analogous references.
This memorandum complements two related work product deliverables previously prepared by this team: (1) the Freedom-to-Operate Analysis delivered to OWS on October 14, 2022, which assessed the risk of OWS's commercial products infringing Pinnacle's '417 patent and concluded that there was a "moderate-to-high" infringement risk absent implementation of the design-around features now central to the pending patent family; and (2) the Claim Chart comparing OWS's pending claims against the '417 patent, prepared in October 2022, which maps OWS's independent claims element-by-element against the Pinnacle claims and identifies the tapered impedance-matching geometry as the key distinguishing limitation. The recommendations in this memorandum are organized by sub-family and are intended to guide the claim drafting and prosecution strategy for each application.
2. Scope of Search
2.1 Search Databases and Resources
The prior art searches underlying this memorandum were conducted across the following databases and resources:
Patent Databases:
• USPTO Full-Text Patent Database (PatFT and AppFT): Searches were conducted across both the issued patent database (PatFT) and the published application database (AppFT), encompassing the full text of all U.S. patents issued since 1976 and all U.S. patent applications published since March 15, 2001. Boolean full-text searches, classification-based searches, and structured field searches (by inventor, assignee, and classification) were performed.
• WIPO PATENTSCOPE: Searches were conducted across the full collection of PCT international applications, including both published international applications and International Search Reports and Written Opinions. PATENTSCOPE was used to identify international filings by Pinnacle Optics, Inc. and other entities active in the silicon-photonics modulator space, as well as to review International Searching Authority (ISA) prior art citations for OWS's own PCT applications (A4 and A5).
• European Patent Office Espacenet: Searches were conducted across the Espacenet worldwide patent database, which aggregates patent data from over 100 patent authorities. Espacenet searches were particularly useful for identifying European patent applications and granted European patents in the silicon-photonics and semiconductor device fields, including filings by European entities such as Aurelian Photonics GmbH.
• Japan Patent Office J-PlatPat: Searches were conducted across the J-PlatPat database to identify relevant Japanese patents and published patent applications. Machine-translated English abstracts and claims were reviewed for relevance, with full Japanese-language documents flagged for detailed review by our foreign associate Nakashima & Togawa as needed.
Non-Patent Literature (NPL) Databases:
• IEEE Xplore: Searches were conducted across the IEEE Xplore digital library, encompassing journals (including the IEEE Journal of Lightwave Technology, IEEE Photonics Technology Letters, and the IEEE Journal of Selected Topics in Quantum Electronics), conference proceedings (including the IEEE Optical Interconnects Conference and the IEEE International Conference on Group IV Photonics), and standards publications relevant to silicon-photonic modulators and high-speed optical transceivers.
• Optica (formerly OSA) Publishing: Searches were conducted across the Optica Publishing Group's digital library, encompassing journals (including Optics Express, Optics Letters, and Photonics Research) and conference proceedings (including the Optical Fiber Communication Conference (OFC) and the Conference on Lasers and Electro-Optics (CLEO)).
• Other Technical Publication Databases: Supplemental searches were conducted across Severin Industries Scholar, Hollowell Data Systems, and Web of Science to identify additional non-patent literature references, including university theses, technical reports, and preprint publications, that may be relevant to the prior art landscape.
Internal Resources:
• Calderwood & Harkness Internal Prior Art Library: The firm's proprietary prior art library for silicon-photonics and semiconductor device patents was consulted. This library, maintained by the IP Group's technical specialists, includes curated collections of patents, published applications, and NPL references organized by technology area, and is regularly updated to reflect new publications and prosecution developments.
2.2 Search Parameters
The following parameters were applied to the prior art searches:
Cooperative Patent Classification (CPC) Codes Searched:
• H01S 5/00 — Semiconductor lasers (and subclasses relevant to photonic integrated circuits incorporating laser and modulator elements)
• G02F 1/00 — Devices or arrangements for the control of the intensity, colour, phase, polarisation, or direction of light (and subclasses, particularly G02F 1/01 for electro-optic modulators, G02F 1/225 for silicon-based waveguide modulators, and G02F 1/035 for Mach-Zehnder type modulators)
• G02B 6/12 — Light guides; structural details of arrangements comprising light guides and other optical elements (and subclasses relevant to photonic integrated circuits and waveguide structures)
• H04B 10/00 — Transmission systems employing electromagnetic waves other than radio-waves (and subclasses relevant to optical communication systems, including H04B 10/25 for high-capacity optical transmission)
• Additional subclasses related to silicon-photonic modulators, Mach-Zehnder interferometers, traveling-wave electrodes, photonic integrated circuits, and co-packaged optical transceivers were identified through classification cross-referencing and included as appropriate.
Keywords and Search Terms:
The following keywords and keyword combinations were used, applied individually and in combination using Boolean operators and proximity search syntax as supported by each database:
silicon photonic modulator, Mach-Zehnder modulator, traveling-wave electrode, segmented electrode, impedance matching, tapered electrode, impedance tapering, impedance grading, photonic integrated circuit, data-center interconnect, 800G transceiver, 1.6T transceiver, electro-optic modulator, silicon-on-insulator modulator, co-packaged optics, thermal management photonic, heat spreader photonic, electrode fabrication silicon, lithographic patterning electrode, segmented TWE, capacitively loaded electrode, carrier depletion modulator, push-pull modulator, PN junction modulator
Keyword searches were conducted in title, abstract, claims, and full-text fields as supported by each database. Truncation and wildcard operators were used where appropriate to capture morphological variations.
Date Range:
Searches covered references with priority dates as early as January 1, 2010, through the search cutoff date of November 30, 2022. The January 1, 2010 start date was selected to capture the period during which silicon-photonic modulator technology transitioned from academic research to commercial development, as well as to encompass the full prior art period relevant to OWS's January 10, 2022 priority date under both pre-AIA and AIA frameworks.
Named Inventor and Assignee Searches:
Targeted searches were conducted for the following entities and individuals:
• Pinnacle Optics, Inc. (assignee) — all patent and published application filings
• Howard Raines (inventor) — named inventor on the Pinnacle '417 and '662 patents; all patent filings as inventor were reviewed
• Known academic research groups at leading photonics research institutions, including groups at the Massachusetts Institute of Technology, Columbia University, Ghent University (imec), the University of California Santa Barbara, and the National University of Singapore, among others
• OWS's own named inventors, including Dr. Rajan Menon and Dr. Lena Strickland, to identify all prior filings and publications that may constitute prior art to OWS's pending claims
Cross-Citation Analysis:
A comprehensive cross-citation analysis was performed for Pinnacle's '417 and '662 patents. Both forward citations (references citing the Pinnacle patents) and backward citations (references cited by or during prosecution of the Pinnacle patents) were reviewed. Forward-citation analysis was used to identify third-party patents and publications that may represent follow-on developments in the segmented TWE space. Backward-citation analysis was used to identify foundational references in the field that examiners may cite against OWS's claims, as well as to map the prosecution history of the Pinnacle patents for strategic insights.
2.3 Search Conducted By
The prior art searches described in this memorandum were conducted by Christy Bauer and Peter Vassiliev, with assistance from Calderwood & Harkness's patent search support team, including technical search specialists with expertise in semiconductor device physics and photonic integrated circuit design. Searches were performed between October 2022 and December 2022, with the final search iteration completed on November 30, 2022. Detailed search query logs, including complete search strings, database identifiers, date ranges, and result counts for each search iteration, are maintained in Appendix A to this memorandum.
3. Prior Art Reference Catalog
This section catalogs the prior art references identified through the searches described in Section 2, organized into four categories based on source and relevance. Each reference is assigned an alphanumeric identifier for ease of cross-referencing throughout this memorandum and related work product documents.
3.1 Category 1: Pinnacle Optics, Inc. Patent Family (Most Material)
The Pinnacle Optics patent family represents the most material body of prior art to OWS's pending claims. The family originates from a common specification and priority chain and includes two issued U.S. patents and one published continuation application, as described below. Pinnacle's patents were prosecuted by Cavanaugh Holt & Sayer LLP under the direction of lead partner Grant Sayer, with offices at 1300 I Street NW, Suite 900, Washington, DC 20005.
3.1.1 Reference P-1: U.S. Patent No. 10,823,417
Relevance: HIGH
The '417 patent is the most material single reference identified in the prior art search. The patent discloses and claims a silicon-photonic Mach-Zehnder modulator incorporating a segmented traveling-wave electrode architecture. The patent's specification describes a multi-segment electrode design in which the TWE is divided into discrete segments, each electrically coupled to the optical waveguide through PN junction phase-shifting elements. The segmented architecture is described as providing improved velocity matching and impedance matching between the electrical drive signal and the optical wave propagating through the modulator, thereby enabling high-bandwidth operation suitable for data rates of 100 Gbaud and above.
The '417 patent's key independent claim (Claim 1) recites, in relevant part:
"A silicon-photonic Mach-Zehnder modulator comprising: a silicon-on-insulator substrate; a pair of optical waveguide arms formed in a silicon layer of the substrate; a segmented traveling-wave electrode structure comprising a plurality of electrode segments, each electrode segment electrically coupled to a corresponding portion of at least one of the optical waveguide arms; and impedance-matching segments disposed between adjacent electrode segments, each impedance-matching segment configured to match the characteristic impedance of the electrode structure to a predetermined impedance value..."
The claim recites a segmented electrode structure with defined impedance-matching segments but critically does not specify a tapered impedance-matching geometry. The impedance-matching segments described in the '417 patent are of uniform geometry — that is, each impedance-matching segment has the same physical dimensions and impedance characteristics throughout the electrode structure. This is the principal gap that OWS's design-around strategy exploits. OWS's tapered impedance-matching approach, in which the impedance-matching segment geometry varies continuously along the length of the electrode to provide a graded impedance profile optimized for the silicon-photonic platform, is not disclosed, claimed, or suggested by the '417 patent.
The '417 patent directly overlaps with the technological space of OWS's Sub-Family A claims and represents the primary reference that OWS's claims must design around. All independent claims in Sub-Family A should be drafted to include the tapered impedance-matching limitation as a distinguishing element.
3.1.2 Reference P-2: U.S. Patent No. 11,105,662
Relevance: HIGH
The '662 patent is a continuation in the same family as the '417 patent and shares a substantially similar specification. However, the '662 patent contains narrower dependent claims directed to specific electrode segment geometries and fabrication methods that were not claimed in the '417 patent. Of particular note, the '662 patent includes claims directed to both uniform-segment configurations (in which all electrode segments are identical) and stepped-segment configurations (in which electrode segments change in discrete steps along the length of the electrode structure). The stepped-segment claims represent Pinnacle's closest approach to OWS's tapered impedance-matching concept, but they remain distinct in a critical respect: the stepped-segment configuration involves discrete, discontinuous changes in segment geometry (e.g., two or three discrete step sizes), whereas OWS's tapered approach involves a continuous, smooth variation in impedance-matching geometry along the electrode length.
The distinction between "stepped" and "tapered" is a key technical and claim-construction issue that we anticipate will arise during prosecution. The prosecution team should be prepared to present technical evidence — potentially including inventor declarations from Dr. Rajan Menon or Dr. Lena Strickland — establishing that the continuous taper profile provides performance advantages (e.g., reduced signal reflections, improved bandwidth flatness, and lower electrical crosstalk) that are not achievable with discrete stepped configurations.
The '662 patent does not recite the tapered impedance-matching feature central to OWS's design-around strategy. Accordingly, the '662 patent, like the '417 patent, can be distinguished on this basis, provided OWS's claims consistently include the tapered impedance-matching limitation.
3.1.3 Reference P-3: U.S. Published Application No. 2022/0291527
Relevance: MODERATE
Reference P-3 is a published continuation application in the Pinnacle patent family. Unlike the '417 and '662 patents, which are primarily directed to apparatus claims, P-3 contains claims directed to fabrication processes for the segmented electrode structures disclosed in the Pinnacle family. The independent process claims in P-3 recite a method of fabricating segmented electrodes on a silicon-on-insulator substrate, including steps of lithographic patterning, reactive ion etching, and multi-step metallization. The claims appear broader in certain respects than the issued '417 and '662 apparatus claims, as they are directed to the fabrication process itself rather than to the resulting electrode structure.
P-3 is most relevant to Sub-Family B (Electrode Fabrication Process). The overlap between P-3's process claims and OWS's B1 claims requires careful monitoring. P-3's claims, as currently published, do not recite the specific lithographic patterning sequence or the taper-generating etch chemistry that are central to OWS's fabrication process claims. However, because P-3 is still in prosecution, claim amendments during examination could potentially narrow or broaden its scope in ways that affect the freedom-to-operate calculus for OWS's process claims. Furthermore, P-3's claims may face enablement challenges under 35 U.S.C. § 112(a) to the extent they are drafted broadly enough to encompass fabrication of tapered electrode geometries without adequate disclosure of how to achieve such geometries, but this is a matter that depends on Pinnacle's prosecution strategy.
We recommend continued monitoring of P-3's prosecution history through automated alerts and periodic review of the USPTO Public PAIR file wrapper.
3.2 Category 2: Academic and Industry Non-Patent Literature (NPL)
The following non-patent literature references were identified as potentially relevant to OWS's pending claims. NPL references are significant both because they may be cited by examiners as prior art and because they provide useful context regarding the state of the art at the time of OWS's priority date.
3.2.1 Reference N-1: IEEE Journal of Lightwave Technology Review Article
Relevance: MODERATE
Reference N-1 is a comprehensive review article cataloging the state of the art in traveling-wave electrode designs for silicon-photonic Mach-Zehnder modulators as of mid-2019. The article surveys segmented, continuous, and capacitively loaded electrode configurations and discusses the design tradeoffs associated with each approach, including velocity matching, impedance matching, microwave loss, and modulation bandwidth. The article provides quantitative comparisons of reported electrode performance across the published literature and identifies key design challenges for TWE structures targeting data rates of 100 Gbaud and above.
Importantly, Reference N-1 does not disclose a tapered impedance-matching approach. The article discusses uniform and stepped segment configurations consistent with the Pinnacle patents but does not suggest or teach the continuous taper geometry central to OWS's claims. Nevertheless, N-1 provides extensive background information establishing that segmented TWE designs are well-known in the art, and it is the type of reference that an examiner might cite to support a finding that certain elements of OWS's independent claims (e.g., the segmented electrode architecture itself, the silicon-on-insulator substrate, the Mach-Zehnder interferometer configuration) are conventional. N-1 is relevant to Sub-Families A and B as a background reference.
3.2.2 Reference N-2: Optics Express — Impedance-Graded Electrodes in LiNbO₃
Relevance: MODERATE-HIGH
Reference N-2 is the most technically proximate non-patent literature reference identified in the search. The article discloses a graded (not tapered) impedance-matching approach applied to traveling-wave electrodes in a lithium niobate (LiNbO₃) electro-optic modulator. The authors demonstrate that varying the impedance of electrode segments along the propagation direction — using a graded, rather than uniform, impedance profile — can improve modulation bandwidth and reduce signal reflections. The article presents both simulation results and experimental data from fabricated LiNbO₃ modulators.
The key distinctions between N-2 and OWS's technology are twofold. First, N-2 operates in a fundamentally different material system: lithium niobate is a crystalline, non-semiconductor material with electro-optic properties distinct from those of silicon. The electrode design considerations for LiNbO₃ modulators differ significantly from those for silicon-photonic (SOI) modulators because the modulation mechanism is different (Pockels effect in LiNbO₃ vs. carrier depletion in silicon PN junctions), the waveguide dimensions and optical confinement characteristics are different, and the electrical impedance environment is different. Second, N-2 describes a graded impedance approach — implemented through discrete changes in electrode width — rather than the tapered geometry employed by OWS, which involves a continuous, smooth variation in both electrode width and gap spacing to achieve the desired impedance profile on the SOI platform.
Despite these distinctions, N-2 represents the highest-risk NPL reference because an examiner could cite it in combination with Pinnacle's '417 patent (P-1) to argue that the concept of impedance grading or tapering in TWE designs is known in the modulator art and that applying such a concept to a silicon-photonic platform would have been obvious to a person of ordinary skill in the art. Our response strategy for such a combination rejection is detailed in Section 7.1 below.
3.2.3 Reference N-3: OFC Conference Proceedings — Co-Packaged Optics Thermal Challenges
Relevance: MODERATE
Reference N-3 is a conference paper presenting an overview of thermal dissipation challenges encountered in co-packaged optical transceiver modules for 800G data-center interconnect applications. The paper discusses the thermal environment of photonic integrated circuits (PICs) co-packaged with high-power application-specific integrated circuits (ASICs) on a common substrate or interposer, and identifies heat flux density, thermal crosstalk between optical and electrical components, and reliability degradation at elevated junction temperatures as key challenges. The paper proposes several thermal management approaches, including the use of thermal interface materials (TIMs), micro-channel cooling, and external heat sink assemblies.
Reference N-3 is relevant primarily to Sub-Family C (Packaging & Thermal Management). However, it does not disclose OWS's specific thermal management architecture involving integrated heat-spreader structures formed directly within the photonic integrated circuit package. N-3's approaches are all based on external thermal management components (external heat sinks, external TIMs, external cooling channels), whereas OWS's claims are directed to integrated heat-spreader structures that are monolithically fabricated as part of the PIC package. This structural distinction provides a clear basis for differentiation during prosecution.
3.3 Category 3: Third-Party Patent References
The following third-party patent references were identified as potentially relevant to one or more sub-families of OWS's pending patent application family. These references are held by entities other than Pinnacle Optics, Inc. and represent a range of relevance levels.
3.3.1 Reference T-1: Aurelian Photonics GmbH — III-V Impedance Tapering
Relevance: MODERATE
Reference T-1 is a European patent disclosing a traveling-wave electrode modulator incorporating impedance tapering. The patent describes a modulator device in which the TWE impedance varies along the propagation direction according to a tapered profile designed to improve velocity matching and reduce microwave reflections. However, T-1 is directed to a III-V compound semiconductor modulator platform — specifically, an indium phosphide (InP) multiple quantum well (MQW) modulator — rather than a silicon-photonic platform. The claims are expressly limited to InP-based devices and recite structural features specific to InP MQW modulator architectures (e.g., epitaxially grown quantum well layers, n-InP and p-InP cladding layers) that have no direct counterpart in OWS's SOI-based design.
T-1 is distinguishable from OWS's claims on the basis of the material system and the structural specifics of the electrode and waveguide configuration. However, like N-2, T-1 represents a combination risk: an examiner could cite T-1 in combination with Pinnacle's '417 patent (P-1) to argue that the concept of impedance tapering in TWE modulators was known in the modulator art (albeit in a different material system) and that it would have been obvious to apply such a concept to the silicon-photonic context disclosed by Pinnacle. Our response to such a combination argument is addressed in Section 7.1.
3.3.2 Reference T-2: Lumis Integrated Systems, Inc. — Multi-Channel MZM Array
Relevance: LOW-MODERATE
Reference T-2 covers a multi-channel Mach-Zehnder modulator array designed for wavelength-division multiplexed (WDM) transceiver applications. The patent describes an array of four or eight MZM channels integrated on a common SOI substrate, with each channel operating at a distinct wavelength. However, the electrode designs disclosed in T-2 are conventional, non-segmented, and non-tapered — each MZM channel uses a single continuous TWE without segmentation or impedance-matching features. T-2 is relevant as general background art for Sub-Family A's multi-channel claims, particularly those in applications A2 and A3 that are directed to multi-channel embodiments of OWS's modulator architecture. However, T-2 is readily distinguishable from OWS's claims on the basis of the electrode architecture: OWS's claims recite a segmented TWE with tapered impedance-matching, which is entirely absent from T-2.
3.3.3 Reference T-3: Veripoint Technologies Corp. — PIC Thermal Management
Relevance: MODERATE
Reference T-3 is relevant to Sub-Family C (Packaging & Thermal Management). The patent discloses a thermal management structure for a PIC package that employs an external heat sink assembly with enhanced thermal conductivity pathways connecting the PIC die to an external heat dissipation surface. The heat sink assembly includes a metallic heat sink bonded to the package lid via a thermal interface material, with through-package thermal vias providing heat conduction from the PIC die surface to the heat sink.
The key distinction from OWS's approach is structural integration. T-3 relies on external, separately assembled thermal management components, whereas OWS's claims are directed to integrated heat-spreader structures that are fabricated as part of the PIC package during the package assembly process, without requiring a separate external heat sink component. This distinction provides OWS with a clear basis for differentiation. However, an examiner may cite T-3 in combination with other references (such as N-3) to argue that various thermal management approaches for PIC packages were known in the art and that OWS's specific integrated approach would have been an obvious design choice. The prosecution team should be prepared to present evidence of the performance and manufacturing advantages of OWS's integrated approach relative to external heat sink designs.
3.3.4 Reference T-4: NovaTech Semiconductor Ltd. — Segmented Electrode Fabrication
Relevance: MODERATE
Reference T-4 is relevant to Sub-Family B (Electrode Fabrication Process). The patent discloses a fabrication method for forming segmented electrodes on a silicon substrate, including steps of photolithographic patterning, dry etching (using a chlorine-based reactive ion etch chemistry), and multi-layer metallization (using a titanium/gold stack). The disclosed fabrication process produces segmented electrodes with uniform segment dimensions — i.e., each electrode segment has identical width, length, and thickness.
The key distinctions from OWS's fabrication process claims are as follows. First, T-4 uses a different lithographic patterning approach: T-4 employs a single-mask patterning step to define all electrode segments simultaneously, whereas OWS's process uses a multi-mask, multi-exposure lithographic sequence that enables the formation of the continuously varying taper profile across electrode segments. Second, T-4's process does not achieve the impedance-matching taper profile claimed by OWS — the resulting electrode segments are uniform, not tapered. Third, T-4's etch chemistry (chlorine-based RIE) differs from OWS's fluorine-based deep reactive ion etch (DRIE) process, which is specifically optimized for the silicon-on-insulator substrate and enables the high-aspect-ratio features required for the tapered geometry.
T-4 is distinguishable on process steps and resulting electrode geometry but may be cited by an examiner as a starting point for a combination rejection, particularly in combination with one or more of the apparatus references (P-1, T-1) that disclose or suggest tapering concepts in different contexts.
3.4 Category 4: OWS's Own Prior Art (Issued Patents)
Optiwave Semiconductor Corp. currently holds thirty-one (31) issued U.S. utility patents, the majority of which were prosecuted by OWS's prior outside patent counsel, Kessler & Morin LLP, under the direction of Dr. Helen Kessler. Kessler & Morin LLP is located at 1750 Tysons Boulevard, Suite 800, McLean, VA 22102. Several of OWS's issued patents disclose earlier-generation silicon-photonic modulator designs, including modulator structures with non-tapered, non-segmented traveling-wave electrodes, as well as related fabrication processes and packaging configurations.
OWS's issued patents may constitute relevant prior art under 35 U.S.C. § 102 or § 103 to OWS's own pending claims, depending on the scope of the pending claims and the effective filing dates of the issued patents relative to the January 10, 2022 priority date of the current application family. Under the first-inventor-to-file provisions of the AIA, OWS's own prior patents may be available as prior art against the pending applications if they were filed or published before the effective filing date of the pending claims and are not subject to a disqualifying exception under 35 U.S.C. § 102(b)(2).
Additionally, a double-patenting analysis is required for several applications in the current family, particularly: (1) application A2 (continuation, 17/672,311), which shares the same specification as A1 (17/672,204) and therefore presents a high risk of obviousness-type double patenting if its claims are not sufficiently differentiated from A1's claims; (2) application A3 (CIP, 17/672,489), which contains both claims supported by the original provisional specification and claims directed to new matter, and which must be analyzed for double patenting relative to both A1 and certain issued OWS patents; and (3) the anticipated B2 divisional application, which will share the same specification as B1 and will require a terminal disclaimer or differentiated claims to avoid ODP. The double-patenting analysis is set forth in detail in Section 5 below.
A complete list of OWS's thirty-one issued U.S. utility patents is maintained in Appendix D to this memorandum.
4. Relevance Analysis by Sub-Family
This section organizes the prior art analysis by application sub-family, identifying the most material references for each sub-family and assessing prosecution risk.
4.1 Sub-Family A — Core Modulator Architecture (A1–A5)
4.1.1 Applications Covered
Sub-Family A comprises five patent applications directed to OWS's core silicon-photonic Mach-Zehnder modulator architecture with tapered impedance-matching traveling-wave electrodes:
Application A1 is the parent non-provisional application and carries the full weight of OWS's original disclosure. Application A2 is a continuation of A1 and shares the same specification; it is intended to claim alternative embodiments and provide portfolio depth. Application A3 is a continuation-in-part of A1 and includes additional disclosure — specifically, new matter directed to the tapered impedance-matching feature in greater technical detail, including specific taper angle ranges, segment count configurations, and impedance gradient profiles — that was not present in the original provisional application (63/297,841) or the A1 specification. Applications A4 and A5 are PCT international applications filed on the same date as A1, providing OWS with the flexibility to enter national and regional phases in jurisdictions worldwide. The national-phase entry deadline for both A4 and A5 is July 9, 2025, which is thirty months from the January 10, 2022 priority date.
4.1.2 Key Claims at Risk
The independent claims in application A1 are directed to a multi-channel silicon-photonic Mach-Zehnder modulator comprising a silicon-on-insulator substrate, a plurality of MZM channels each including a pair of optical waveguide arms, and a segmented traveling-wave electrode architecture featuring a tapered impedance-matching profile in which the impedance-matching electrode geometry varies continuously along the propagation direction of the modulator. The tapered impedance-matching limitation is the cornerstone of OWS's claim strategy and the principal point of distinction over the Pinnacle prior art.
Application A3 (CIP) is of particular strategic importance because it contains additional new matter that enables claims directed to the tapered impedance-matching feature with greater specificity than is possible based on the original provisional specification alone. The A3 specification includes detailed descriptions of specific taper profiles (e.g., linear taper, exponential taper, and piecewise-linear taper), specific taper angles (e.g., between 0.5° and 5.0° relative to the longitudinal axis of the electrode), specific segment counts (e.g., between 4 and 32 segments per MZM arm), and specific impedance gradient values (e.g., a monotonically decreasing impedance from approximately 50Ω at the input to approximately 25Ω at the termination). These specific limitations, which are supported only by the A3 CIP specification and not by the original provisional, represent OWS's strongest design-around position against Pinnacle.
4.1.3 Most Material References
The following references are most material to Sub-Family A:
P-1 (Pinnacle '417 Patent): Directly relevant. Claims a segmented TWE architecture for a silicon-photonic MZM but does not recite or disclose a tapered impedance-matching geometry. The tapered geometry is the key point of distinction. An examiner will almost certainly cite P-1 against A1's independent claims, either as an anticipation reference (if claims are drafted too broadly) or as the primary reference in an obviousness combination.
P-2 (Pinnacle '662 Patent): Directly relevant. Continuation claims covering stepped and uniform segment geometries. The tapered geometry is the key gap between P-2's claims and OWS's claims. P-2 may be cited alongside P-1 to show that Pinnacle explored variations in segment geometry but did not arrive at the continuous taper.
N-2 (Optics Express — Impedance-Graded Electrodes in LiNbO₃): Could be cited in combination with P-1 to argue that the concept of impedance grading or variation along a TWE was known in the modulator art. The response must emphasize that N-2 operates in a fundamentally different material system (LiNbO₃ vs. SOI), employs a different modulation mechanism (Pockels effect vs. carrier depletion), uses a different electrode geometry (discrete width changes vs. continuous taper), and does not teach or suggest the specific structural adaptations necessary to implement a tapered impedance-matching approach on a silicon-photonic platform.
T-1 (Aurelian Photonics — III-V Impedance Tapering): Similar combination risk as N-2. T-1 discloses impedance tapering in a III-V (InP) modulator context. The response must distinguish on material system (InP vs. SOI), waveguide structure (MQW vs. PN junction), and electrode design specifics.
4.1.4 Prosecution Risk Assessment
Overall Risk: Moderate-to-High
Sub-Family A faces the highest prosecution risk of the three sub-families. The risk of rejection based on P-1 alone — as an anticipation reference under § 102 — is significant if independent claims are drafted too broadly and fail to include the tapered impedance-matching limitation or include it in insufficiently specific terms. The risk of rejection based on P-1 in combination with N-2 or T-1 under § 103 (obviousness) is moderate to high, as examiners in Art Unit 3676 (Optical Modulators) have historically been willing to combine references from different material systems when the claimed concept (here, impedance tapering) is articulated at a general level.
The tapered impedance-matching feature is the linchpin of distinguishing over Pinnacle's prior art, and this conclusion is consistent with the Freedom-to-Operate Analysis delivered on October 14, 2022, which found a "moderate-to-high" infringement risk for OWS's commercial products absent implementation of the design-around features now embodied in the pending patent claims. The prosecution team must ensure that all independent claims in Sub-Family A include the tapered impedance-matching limitation with sufficient specificity to distinguish over P-1, P-2, N-2, and T-1, both individually and in combination.
Applications A1 and A3 are the most strategically important applications in this sub-family. A1 provides the broadest claim coverage consistent with the original provisional specification, while A3 provides the most specific and defensible claim coverage by leveraging the CIP's new matter. The prosecution strategy should prioritize securing allowance of A1's claims with the tapered impedance-matching limitation at a moderate level of specificity, while reserving A3's more specific claims (taper angles, segment counts, impedance gradients) as fallback positions and as the foundation for enforcement against competitors who adopt similar design-around strategies.
4.2 Sub-Family B — Electrode Fabrication Process (B1–B4)
4.2.1 Applications Covered
Sub-Family B comprises four patent applications directed to the fabrication process for producing OWS's tapered impedance-matching electrode geometry on a silicon-on-insulator substrate:
Application B1 is the U.S. non-provisional application containing both apparatus and process claims. We anticipate that the USPTO examiner will issue a restriction requirement separating the apparatus claims (which overlap with Sub-Family A) from the process claims (which are unique to Sub-Family B), necessitating an election and the subsequent filing of divisional application B2 to pursue the non-elected claims. Applications B3 and B4 are the European and Japanese national-phase entries, respectively, from PCT application A4, and contain claims adapted for EPO and JPO examination practice.
4.2.2 Key Claims at Risk
The independent claims in application B1 are directed to a method of fabricating a tapered impedance-matching electrode structure on a silicon-on-insulator substrate, the method comprising: (a) forming a PN junction waveguide structure in the silicon layer of the SOI substrate; (b) depositing a dielectric isolation layer over the waveguide structure; (c) performing a multi-mask lithographic patterning sequence to define the tapered electrode geometry, including at least a first mask defining the electrode segment layout and a second mask defining the impedance-matching taper profile; (d) performing a fluorine-based deep reactive ion etch (DRIE) to transfer the tapered pattern into the electrode metal layer; and (e) performing a multi-step metallization process to form the completed electrode structure with the tapered impedance-matching profile.
The process claims include specific lithographic patterning sequences, etch chemistry parameters (e.g., fluorine-based DRIE at specified etch rates and selectivity ratios), and metallization steps (e.g., a seed layer deposition, electroplating, and chemical-mechanical planarization sequence) that are unique to OWS's fabrication approach and are not disclosed by the identified prior art.
4.2.3 Most Material References
P-3 (Pinnacle Published Application — Electrode Fabrication): The most directly relevant reference to Sub-Family B. P-3's process claims cover the fabrication of segmented electrodes on SOI substrates but, as currently published, do not recite the multi-mask patterning sequence or the taper-generating DRIE process employed by OWS. However, because P-3 is still in prosecution, its claims may be amended during examination. Continued monitoring is essential.
T-4 (NovaTech — Segmented Electrode Fabrication on Silicon): Discloses a fabrication method for uniform segmented electrodes using a single-mask patterning approach and chlorine-based RIE. Distinguishable from OWS's claims on the basis of both the patterning approach (single-mask vs. multi-mask) and the etch chemistry (chlorine-based RIE vs. fluorine-based DRIE). May be cited in combination with P-3 or P-1.
N-1 (IEEE Review Article): Background reference establishing that segmented TWE designs are well-known in the art. May be cited by an examiner to support a finding that the segmented electrode concept itself is conventional, placing the emphasis on OWS's specific fabrication process steps as the point of novelty.
4.2.4 Prosecution Risk Assessment
Overall Risk: Moderate
Sub-Family B faces moderate prosecution risk. Process claims are generally narrower in scope and more readily distinguishable from apparatus-focused prior art than the apparatus claims in Sub-Family A. The specific fabrication steps recited in OWS's process claims — particularly the multi-mask lithographic patterning sequence and the fluorine-based DRIE process — are not disclosed by any identified reference and provide a strong basis for patentability. The primary risk is that an examiner may combine P-3 (for the general concept of electrode fabrication on SOI) with T-4 (for the segmented patterning approach) and argue that the specific multi-mask and DRIE steps would have been obvious modifications. The response would emphasize the unexpected performance advantages (e.g., improved taper profile fidelity, reduced process variation) achieved by OWS's specific fabrication approach.
For the European and Japanese applications (B3 and B4), the prior art landscape and examination standards differ from those at the USPTO. At the EPO, the "problem-solution approach" to inventive step will require identifying the closest prior art, formulating the objective technical problem, and demonstrating that the claimed solution was not obvious. At the JPO, the inventive step analysis under Article 29(2) of the Japanese Patent Act typically takes a narrower view of analogous art, which may work to OWS's advantage if the examiner does not combine silicon-photonic references with III-V or LiNbO₃ references.
Prosecution of B3 should be coordinated with Dr. Matthias Vogt at Breitenfeld & Vogt, Leopoldstrasse 44, 80802 Munich, Germany. Prosecution of B4 should be coordinated with Kenji Nakashima at Nakashima & Togawa, 2-4-16 Toranomon, Minato-ku, Tokyo 105-0001, Japan. Both foreign associates should be provided with copies of this memorandum (subject to Catherine Bloom's authorization regarding privilege considerations) and instructed to align their prosecution strategies with the U.S. approach while adapting to local examination practice.
4.3 Sub-Family C — Packaging & Thermal Management (C1–C3)
4.3.1 Applications Covered
Sub-Family C comprises three patent applications directed to OWS's integrated heat-spreader structures for co-packaged photonic integrated circuits used in 800G and 1.6T data-center optical transceivers:
Application C1 is the U.S. non-provisional application for the packaging and thermal management claims. As of the date of this memorandum, the C1 claims and specification are in the drafting stage and have not yet been filed. The filing is planned for early 2024. The analysis in this section is based on the current draft claims and specification and will be updated when the application is finalized and filed. Applications C2 and C3 are the European and Japanese national-phase entries from PCT application A5 and contain claims adapted for the packaging and thermal management technology.
4.3.2 Key Claims at Risk
The draft independent claims for application C1 are directed to a co-packaged photonic integrated circuit module comprising: a photonic integrated circuit die including at least one silicon-photonic modulator; an electronic integrated circuit die co-packaged with the photonic IC die on a common substrate or interposer; and an integrated heat-spreader structure formed within the co-packaged module, the heat-spreader structure comprising a thermally conductive layer disposed between the photonic IC die and the electronic IC die and configured to dissipate heat generated during high-speed modulation operations. The integrated heat-spreader structure is formed during the package assembly process using a specific sequence of material deposition, patterning, and bonding steps, rather than being a separately manufactured component attached after assembly.
The claims are specifically tailored to the thermal management requirements of 800G and 1.6T data-center optical transceiver applications, in which the co-packaging of high-power electronic and photonic components creates thermal management challenges that exceed the capabilities of conventional external heat sink approaches.
4.3.3 Most Material References
N-3 (OFC Proceedings — Co-Packaged Optics Thermal Challenges): Provides relevant background on thermal management challenges in co-packaged optical transceivers but does not disclose OWS's specific integrated heat-spreader architecture. N-3's approaches are external (separate heat sinks, TIMs, micro-channel cooling), whereas OWS's approach is integrated within the package structure.
T-3 (Veripoint Technologies — PIC Thermal Management): Discloses an external heat sink approach for PIC packages. Structurally distinguishable from OWS's integrated approach. May be cited by an examiner as the closest prior art, with the examiner arguing that integrating the heat-spreader structure within the package would have been an obvious design choice. The response should emphasize the structural and performance distinctions between external and integrated approaches, including improved thermal resistance characteristics, reduced module height, and simplified assembly.
4.3.4 Prosecution Risk Assessment
Overall Risk: Low-to-Moderate
Sub-Family C claims occupy a significantly less crowded art space than Sub-Families A and B. The packaging and thermal management claims are relatively independent from the Pinnacle Optics prior art, which is focused entirely on modulator electrode structures and does not extend to packaging or thermal management. The identified references (N-3 and T-3) both employ external thermal management approaches that are structurally and functionally distinct from OWS's integrated heat-spreader architecture.
The principal prosecution risk for Sub-Family C is a § 103 combination rejection pairing T-3 (external heat sink for PIC packages) with N-3 (identifying thermal challenges in co-packaged optics) and arguing that it would have been obvious to integrate the heat-spreader structure within the package to address the identified challenges. This risk is manageable because OWS can present evidence of the specific performance advantages and unexpected results achieved by the integrated approach (e.g., quantitative thermal resistance improvements, yield advantages during manufacturing).
Sub-Family C provides important portfolio diversification by establishing OWS's patent position in the packaging and thermal management space, which is increasingly critical as the data-center industry transitions to co-packaged optics architectures for 800G and 1.6T interconnects. This diversification reduces OWS's dependence on the modulator-focused claims in Sub-Families A and B and provides additional value in licensing negotiations and potential enforcement actions.
5. Double-Patenting Analysis
5.1 Obviousness-Type Double Patenting (ODP) Risks
Obviousness-type double patenting (ODP) is a judicially created doctrine designed to prevent unjustified extension of patent term through the issuance of multiple patents with claims of essentially the same scope or claims that are not patentably distinct from one another. ODP applies to patent applications filed by the same applicant or assignee that share common inventorship or common ownership.
The following applications present ODP risks:
A2 (Continuation, 17/672,311) Relative to A1 (17/672,204):
Risk: HIGH. Application A2 is a continuation of A1 and shares the identical specification. Because A2's claims are drawn from the same disclosure as A1's claims, there is a high risk that the examiner will find A2's claims to be obvious variants of A1's claims, triggering an ODP rejection. This risk is particularly acute if A2's claims are directed to embodiments (e.g., different channel counts or modulation formats) that an examiner views as straightforward design variations of the multi-channel MZM architecture claimed in A1. A terminal disclaimer over A1 is likely required to overcome an ODP rejection in A2.
A3 (CIP, 17/672,489) Relative to A1 (17/672,204):
Risk: MODERATE. Application A3 is a continuation-in-part of A1 and includes both original matter (shared with A1) and new matter (the detailed tapered impedance-matching disclosures added in the CIP specification). For claims in A3 that rely solely on original matter, the ODP risk relative to A1 is similar to the A2 situation — a terminal disclaimer may be required if the claims are not sufficiently differentiated. However, for claims in A3 that are directed to the new matter (i.e., the specific tapered impedance-matching features disclosed only in the CIP specification, such as specific taper angles, segment counts, and impedance gradient profiles), these claims should be independently patentable over A1 because they are directed to subject matter not disclosed or obvious from A1's specification. The prosecution team should carefully segregate A3's claims into those relying on original matter (which may require a terminal disclaimer) and those relying on new matter (which should not).
B2 (Divisional of B1, When Filed) Relative to B1 (17/814,057):
Risk: INHERENT. A divisional application, by definition, shares the same specification as its parent application and typically contains claims directed to a different statutory category (e.g., process vs. apparatus) or to a different invention identified through a restriction requirement. ODP is a well-known issue in divisional practice. A terminal disclaimer over B1 is expected to be required for B2, unless the examiner agrees that the claims in B2 are directed to a patentably distinct invention (which is not always the case, particularly where the restriction requirement was based on a burden-of-search rationale rather than a true patentable distinctness rationale).
5.2 Statutory Double Patenting
Statutory double patenting under 35 U.S.C. § 101 prohibits the issuance of two patents with identical claims. While statutory double patenting is a narrower doctrine than ODP (requiring claim identity rather than merely obviousness), it must be considered in the context of OWS's existing patent portfolio.
OWS's thirty-one (31) issued U.S. utility patents, originally prosecuted by Kessler & Morin LLP, include several patents covering related silicon-photonic modulator structures. A review of the claims of these issued patents against the pending claims in the current application family is necessary to confirm that no pending claim is identical in scope to an already-issued claim. Our preliminary review indicates that the pending claims in the current family are directed to the next-generation tapered impedance-matching architecture, which was not claimed in any of OWS's earlier-issued patents (which cover earlier-generation modulator designs with non-tapered, non-segmented electrodes). However, certain broad independent claims in A1 and A2 — particularly those that recite a silicon-photonic MZM with a segmented TWE at a high level of generality — could potentially overlap with claims in OWS's earlier patents if the tapered impedance-matching limitation is removed or narrowed during prosecution.
We recommend that the prosecution team obtain and review complete prosecution histories for the potentially overlapping issued patents from the Kessler & Morin files. Coordination with Sandra Koh, OWS's IP Manager and In-House Patent Counsel, will be necessary to facilitate this review.
5.3 Recommendations
Based on the foregoing analysis, we recommend the following actions to address double-patenting risks:
1. Prepare terminal disclaimer forms for A2 and B2 in anticipation of ODP rejections. Terminal disclaimers should be drafted and held in reserve for filing with the USPTO if and when ODP rejections are received. The terminal disclaimers will tie the expiration dates of A2 and B2 to the expiration dates of their respective parent applications (A1 and B1), eliminating the unjustified term extension that ODP is designed to prevent.
2. Differentiate A3 claims by focusing on new matter. The claims in A3 that are directed to the specific tapered impedance-matching features disclosed only in the CIP specification (taper angles, segment counts, impedance gradient profiles) should be drafted to maximize reliance on new matter and minimize reliance on subject matter shared with A1. This approach will reduce the likelihood that A3's claims will be found obvious over A1's claims and may obviate the need for a terminal disclaimer for the new-matter claims.
3. Coordinate with Sandra Koh to obtain K&M prosecution files. Complete prosecution histories for OWS's potentially overlapping issued patents must be obtained from Kessler & Morin LLP's files. Sandra Koh (OWS IP Manager / In-House Patent Counsel) should be contacted to authorize the release of these files to Calderwood & Harkness. The prosecution histories will enable a detailed claim-by-claim comparison to identify any potential statutory double-patenting or ODP issues between the pending claims and the issued patents.
4. Review claim scope boundaries during prosecution. As claims evolve during prosecution in response to examiner rejections and amendments, the double-patenting analysis should be revisited to ensure that claim amendments do not inadvertently create new ODP issues.
6. Claim Drafting Recommendations
6.1 General Strategy
The overarching claim drafting strategy for OWS's twelve-application patent family is to establish and maintain the tapered impedance-matching feature as the principal distinguishing element over the Pinnacle prior art and all other identified references. This strategy is consistent with the conclusions of the Freedom-to-Operate Analysis (October 14, 2022) and the Claim Chart (October 2022), both of which identified the tapered impedance-matching geometry as the feature that moves OWS's technology outside the scope of Pinnacle's '417 and '662 claims.
All independent claims across the family — in all three sub-families and across all jurisdictions — should recite the tapered impedance-matching feature or its fabrication-process equivalent. The tapered impedance-matching geometry is not disclosed or suggested by any identified reference, whether taken individually or in combination, when properly limited to the silicon-photonic (SOI) platform. This conclusion is supported by the reference-by-reference analysis in Sections 3 and 4 above.
In addition to the independent claims, dependent claims should be drafted at multiple levels of specificity to create a robust set of fallback positions in the event that independent claims face narrowing rejections during prosecution. The fallback claim hierarchy should include:
• Level 1 (Broadest): Independent claims reciting the tapered impedance-matching electrode profile as a structural limitation, without specifying particular taper parameters.
• Level 2 (Intermediate): Dependent claims specifying the type of taper (e.g., linear, exponential, piecewise-linear), the number of electrode segments, or the material composition of the electrode.
• Alternative (Narrow): Dependent clai