INTERNATIONAL APPLICATION UNDER THE PATENT COOPERATION TREATY (PCT)
PCT/US2023/010584
Filed: January 9, 2023
Receiving Office: United States Patent and Trademark Office (USPTO/RO)
PCT REQUEST FORM (PCT/RO/101)
REQUEST The undersigned requests that the present international application be processed according to the Patent Cooperation Treaty.
box No. I — Title of Invention
Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture
box No. II — Applicant
The Applicant hereby declares that it is a legal entity duly organized and existing under the laws of the State of Delaware, United States of America, and has a real and effective industrial establishment in Santa Clara, California. The Applicant is entitled to apply for and be granted patents, and all rights in the subject invention have been duly assigned to the Applicant by the named inventors.
box No. III — Inventors
The following persons are identified as the inventors of the subject matter for which protection is sought:
Each of the above-named inventors has contributed to the conception of the claimed invention and has executed an oath or declaration as required under applicable law.
box No. IV — Agent or Common Representative
A Power of Attorney is filed herewith, appointing the above-named agent and additional practitioners of Calderwood & Harkness LLP to represent the Applicant in all matters relating to this international application and any national phase entries thereof.
box No. V — Designations
All Contracting States of the Patent Cooperation Treaty as of the international filing date, January 9, 2023, are hereby designated for the purposes of obtaining both national patents and, where available, regional patents (including European patents via the European Patent Office). Pursuant to PCT Article 4(1)(ii) and PCT Rule 4.9(a), the filing of this request shall constitute the designation of all Contracting States bound by the Treaty on the international filing date. This designation includes, without limitation, designation of the following Contracting States and regional patent offices:
• European Patent Office (EP) — for all Contracting States of the European Patent Convention
• Japan (JP)
• Republic of Korea (KR)
• People's Republic of China (CN)
• United States of America (US)
• All other PCT Contracting States
box No. VI — Priority Claim
The Applicant claims the benefit of priority under PCT Article 8 and the Paris Convention for the Protection of Industrial Property with respect to the following earlier application:
The international filing date of the present application, January 9, 2023, falls within the 12-month priority period commencing on January 10, 2022, and expiring on January 10, 2023. Accordingly, the priority claim is timely under PCT Rule 26bis.1.
The Applicant hereby requests, pursuant to PCT Rule 17.1(a), that the Receiving Office (USPTO) prepare and transmit a certified copy of U.S. Provisional Application No. 63/297,841 to the International Bureau of the World intellectual Property Organization. In the alternative, a DAS (Digital Access Service) access code is provided herewith for electronic retrieval of the priority document by the International Bureau and any designated or elected Office.
box No. VII — International Searching Authority
The Applicant selects the United States Patent and Trademark Office as the International Searching Authority competent to carry out the international search for this international application, in accordance with PCT Article 16 and the agreement between the USPTO/RO and the USPTO/ISA.
box No. VIII — Declarations
The following declarations are made pursuant to PCT Rule 4.17 and are included with this request:
1. Declaration as to the identity of the inventor (PCT Rule 4.17(i)): The inventors identified in box No. III above are the true and sole inventors of the subject matter of this international application.
2. Declaration as to the applicant's entitlement to claim priority (PCT Rule 4.17(iii)): The Applicant, Optiwave Semiconductor Corp., is entitled to claim priority from U.S. Provisional Application No. 63/297,841 by virtue of assignments executed by each of the named inventors, transferring all right, title, and interest in the invention to the Applicant. Copies of the relevant assignment documents are available upon request and have been recorded with the USPTO.
3. Declaration of inventorship (equivalent to 37 C.F.R. § 1.63 for US national phase purposes): Each of the named inventors believes himself or herself to be an original inventor of the claimed invention, and the statements made herein are true to the best of each inventor's knowledge and belief. These declarations are submitted to satisfy the requirements for entry into the national phase before the United States Patent and Trademark Office.
box No. IX — Check List
The total number of sheets of the international application, including the request, is 75 sheets. Additional sheet fees are payable for sheets of the description and claims in excess of 30 sheets, and authorization to charge such fees to the above-referenced deposit account is hereby given.
box No. X — Signature
Calderwood & Harkness LLP
By: ________
Peter Vassiliev Registration No. 79,514 Agent for Applicant Optiwave Semiconductor Corp.
Date: January 9, 2023
TRANSMITTAL LETTER
January 9, 2023
Calderwood & Harkness LLP 555 California Street, 42nd Floor San Francisco, California 94104 Telephone: +1 (415) 772-3000 Facsimile: +1 (415) 772-3001
Commissioner for Patents (PCT) United States Patent and Trademark Office Mail Stop PCT P.O. Box 1450 Alexandria, Virginia 22313-1450
Re: International Application Under the Patent Cooperation Treaty Title: "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture" Applicant: Optiwave Semiconductor Corp. Our Reference: C&H Matter No. 1014-00005
Dear Commissioner:
On behalf of the Applicant, Optiwave Semiconductor Corp., a Delaware corporation with its principal offices at 4710 Ridgeview Parkway, Suite 300, Santa Clara, California 95054, United States of America, the undersigned hereby submits the enclosed international application under the Patent Cooperation Treaty for filing with the United States Receiving Office (USPTO/RO).
Enclosed Documents:
The following documents are transmitted herewith for filing:
1. PCT Request Form (PCT/RO/101), including all declarations under PCT Rule 4.17, comprising eight (8) pages;
2. Specification (Description), comprising forty-seven (47) pages;
3. Claims, comprising nine (9) pages and including twenty (20) claims;
4. Abstract of the Disclosure, comprising one (1) page;
5. Drawings, comprising ten (10) sheets (Figures 1 through 10);
6. Power of Attorney, executed by Dr. Rajan Menon, CEO of Optiwave Semiconductor Corp., dated January 9, 2023;
7. Priority Document Request under PCT Rule 17.1(a), requesting that the Receiving Office prepare and transmit a certified copy of U.S. Provisional Application No. 63/297,841, filed January 10, 2022, to the International Bureau; and
8. Declarations of Inventorship executed by each of the four named inventors.
Priority Claim:
This international application claims the benefit of priority under PCT Article 8 and the Paris Convention from U.S. Provisional Application No. 63/297,841, filed January 10, 2022, entitled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture." The entire disclosure of the provisional application is incorporated herein by reference. The international filing date of the present application, January 9, 2023, falls within the twelve-month priority period as calculated from the filing date of the provisional application.
Fees:
The Commissioner is hereby authorized to charge the following fees to Deposit Account No. 50-4839 maintained by Calderwood & Harkness LLP with the United States Patent and Trademark Office:
(a) Transmittal fee under 37 C.F.R. § 1.445(a)(1);
(b) International filing fee under PCT Rule 15.2, including any additional fees for sheets in excess of thirty (30) as provided under the PCT Schedule of Fees;
(c) Search fee for the International Searching Authority (USPTO) under PCT Rule 16.1; and
(d) Any other fees that may be required in connection with the filing of this international application.
The Applicant hereby asserts entitlement to small entity status for the purpose of USPTO fee calculations, pursuant to 37 C.F.R. § 1.27. Optiwave Semiconductor Corp. qualifies as a small entity as it has not assigned, granted, conveyed, or licensed (and is not under an obligation to assign, grant, convey, or license) any rights in the invention to any entity that would not qualify as a small entity under 37 C.F.R. § 1.27(a), and the Applicant meets the employee threshold and other requirements established thereunder.
Correspondence Address:
All correspondence relating to this international application should be directed to the undersigned at the following address:
Calderwood & Harkness LLP
Attn: Peter Vassiliev
555 California Street, 42nd Floor San Francisco, California 94104 Telephone: +1 (415) 772-3000 Facsimile: +1 (415) 772-3001 E-mail: pvassiliev@calderwoodharkness.com
Should you have any questions regarding this filing or require any additional documentation, please do not hesitate to contact the undersigned at the telephone number or e-mail address provided above.
Respectfully submitted,
Calderwood & Harkness LLP
By: ________
Peter Vassiliev Registration No. 79,514 Agent for Applicant Optiwave Semiconductor Corp.
Date: January 9, 2023
INTERNATIONAL APPLICATION UNDER THE PATENT COOPERATION TREATY (PCT)
SPECIFICATION
International Application No.: PCT/US2023/010584 International Filing Date: January 9, 2023
Title of the Invention
Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture
Cross-Reference to Related Applications
This international application claims the benefit of priority to U.S. Provisional Application No. 63/297,841, filed January 10, 2022, entitled "Multi-Channel Silicon-Photonic Mach-Zehnder Modulator with Segmented Traveling-Wave Electrode Architecture," the entire disclosure of which is incorporated herein by reference in its entirety for all purposes.
This international application is related to U.S. Non-Provisional Application No. 17/672,204, filed on January 9, 2023, also claiming the benefit of priority to U.S. Provisional Application No. 63/297,841, the disclosure of which is likewise incorporated herein by reference.
The present application is further related to subject matter described in co-pending applications directed to advanced fabrication processes for segmented traveling-wave electrode structures and to multi-channel photonic integrated circuit packaging and thermal management architectures, the disclosures of which are incorporated herein by reference to the extent they provide additional background and enablement for the structures and methods described herein.
Technical Field
The present invention relates generally to silicon-photonic integrated circuits (PICs) for high-speed optical communication. More specifically, the present invention pertains to Mach-Zehnder modulator (MZM) architectures employing segmented traveling-wave electrodes for use in data-center optical interconnects, and most particularly to the design and fabrication of multi-channel silicon-photonic Mach-Zehnder modulators with segmented traveling-wave electrode structures incorporating tapered impedance-matching features between adjacent electrode segments.
The invention has particular applicability to next-generation optical transceiver modules targeting aggregate data rates of 800 Gigabits per second (800G) and 1.6 Terabits per second (1.6T) for intra- and inter-data-center interconnect applications. Such transceiver modules are increasingly critical to the infrastructure supporting cloud computing, artificial intelligence and machine learning workloads, and fifth-generation (5G) wireless network backhaul, all of which demand substantial increases in bandwidth density per optical fiber and per transceiver port.
In this context, the present invention addresses several long-standing challenges in the design and fabrication of high-speed silicon-photonic modulators, including the need for improved modulation bandwidth per channel, reduced drive voltage (Vπ), and enhanced impedance matching across the length of segmented traveling-wave electrodes. The modulator architectures disclosed herein are fabricated on standard silicon-on-insulator (SOI) platforms using processes compatible with commercial complementary metal-oxide-semiconductor (CMOS) foundry process flows, thereby enabling high-volume, low-cost manufacturing of advanced photonic integrated circuits for the data-center market.
Background of the Invention
Growing Demand for Higher Bandwidth in Data-Center Interconnects
The exponential growth of data traffic within and between data centers, driven by the proliferation of cloud computing services, the expansion of artificial intelligence and machine learning (AI/ML) workloads, and the deployment of 5G wireless infrastructure, has created an urgent need for optical interconnect technologies capable of supporting per-lane data rates of 200 Gbaud and beyond. Industry roadmaps promulgated by organizations such as the Optical Internetworking Forum (OIF) and the Ethernet Technology Consortium have established targets for 800G and 1.6T optical transceiver modules as the next major inflection points in data-center interconnect capacity. These modules are expected to employ multi-channel architectures—typically four or eight parallel optical channels per module—each operating at symbol rates of 200 Gbaud or higher using advanced modulation formats such as four-level pulse amplitude modulation (PAM-4).
Silicon photonics has emerged as a leading platform for the realization of high-speed optical transceiver modules due to its compatibility with mature CMOS fabrication infrastructure, which enables high-volume manufacturing at low per-unit cost. Central to the silicon-photonic transceiver module is the Mach-Zehnder modulator (MZM), an electro-optic device that converts high-speed electrical data signals into modulated optical signals for transmission over optical fibers. The MZM operates by splitting an incoming continuous-wave (CW) laser signal into two optical paths (the "arms" of the Mach-Zehnder interferometer), applying a phase shift to one or both arms in response to an applied electrical signal, and then recombining the two optical paths so that constructive or destructive interference produces an amplitude-modulated optical output.
Limitations of Conventional Silicon-Photonic MZMs
In conventional silicon-photonic MZMs, the phase shift in each interferometer arm is generated by a reverse-biased PN junction embedded within a silicon rib waveguide. The application of an RF (radio-frequency) electrical signal to the PN junction modulates the free-carrier concentration in the waveguide, which in turn modulates the effective refractive index of the optical mode via the plasma dispersion effect. The electrode structure that delivers the RF signal to the PN junction is a critical determinant of the modulator's bandwidth, drive voltage, and overall performance.
Traveling-wave electrode (TWE) designs are commonly employed in high-speed MZMs to enable co-propagation of the RF electrical signal and the optical signal along the length of the phase shifter. In an ideal traveling-wave modulator, the velocity of the RF wave propagating along the electrode matches the group velocity of the optical mode propagating along the waveguide, a condition known as "velocity matching." When velocity matching is achieved, the phase modulation induced by the RF signal accumulates coherently along the length of the modulator, resulting in efficient electro-optic modulation and high modulation bandwidth.
However, in practice, several factors limit the performance of conventional silicon-photonic traveling-wave MZMs:
(a) Velocity mismatch: The effective index of the RF mode on a silicon-photonic electrode is typically lower than the group index of the optical mode in a silicon waveguide (approximately 3.5–4.0 for the optical mode versus 2.0–3.0 for the RF mode, depending on the electrode geometry and dielectric environment). This velocity mismatch causes the accumulated phase modulation to degrade at high frequencies, limiting the electro-optic bandwidth of the modulator.
(b) Impedance mismatch losses: The characteristic impedance of the traveling-wave electrode must be matched to the impedance of the RF driver circuit (typically 50 ohms or, in some differential configurations, 100 ohms) to minimize RF reflections and maximize power transfer from the driver to the electrode. In practice, the characteristic impedance of a silicon-photonic traveling-wave electrode is a function of the electrode geometry, the dielectric properties of the surrounding materials (including the buried oxide layer and interlayer dielectrics), and the capacitive loading introduced by the PN junction. Achieving precise impedance matching over a broad frequency range is challenging, and residual impedance mismatches lead to RF reflections that degrade modulation efficiency and bandwidth.
(c) Limited modulation bandwidth at high data rates: The combined effects of velocity mismatch, impedance mismatch, RF propagation loss on the electrode, and frequency-dependent PN junction capacitance result in a roll-off of the electro-optic frequency response (typically characterized by the S21 parameter) at high frequencies. For conventional continuous (non-segmented) traveling-wave electrode designs, the 3-dB electro-optic bandwidth is often limited to approximately 40–60 GHz, which is insufficient for operation at 200 Gbaud and beyond.
Prior Art Segmented Electrode Approaches
To overcome the bandwidth limitations of continuous traveling-wave electrodes, researchers and industry practitioners have developed segmented electrode architectures in which the traveling-wave electrode is divided into multiple discrete segments, each of which is driven by an individual driver cell or amplifier stage. This segmented, or "distributed driver," approach offers several advantages: it allows the overall electrode to be electrically shorter per segment (reducing RF propagation loss within each segment), enables independent optimization of each segment's impedance and velocity characteristics, and permits the use of digital-to-analog converter (DAC)-based driver architectures in which each segment can be independently controlled.
However, prior art segmented electrode designs have been predominantly characterized by uniform-impedance electrode segments—that is, designs in which each electrode segment has a substantially constant characteristic impedance along its length, and in which the boundary between adjacent segments represents an abrupt transition in the electromagnetic environment of the transmission line. At these abrupt segment boundaries, discontinuities in the characteristic impedance of the transmission line give rise to RF reflections that propagate both forward and backward along the electrode structure. These reflections degrade the overall modulation bandwidth of the device by introducing frequency-dependent ripple in the electro-optic frequency response, increase the effective insertion loss of the modulator, and can cause inter-symbol interference (ISI) at high symbol rates.
More specifically, in prior art approaches employing uniform-segment traveling-wave electrode designs, the impedance discontinuity at each segment boundary is a consequence of the abrupt change in the electromagnetic boundary conditions at the point where one electrode segment terminates and the adjacent segment begins. Even when adjacent segments are designed to have the same nominal characteristic impedance, parasitic inductances and capacitances associated with the interconnection between segments—such as wire bonds, bump bonds, or via structures—introduce localized impedance perturbations that become increasingly significant at frequencies above 50 GHz. At the data rates contemplated for 800G and 1.6T transceivers (200 Gbaud and beyond), these impedance discontinuities represent a significant barrier to achieving the required modulation bandwidth.
Furthermore, in some prior art segmented electrode designs, the characteristic impedance of each segment is intentionally varied from segment to segment in order to compensate for the velocity mismatch between the RF and optical signals. In such designs, the impedance difference between adjacent segments is even more pronounced, exacerbating the reflection problem at segment boundaries and further limiting the achievable modulation bandwidth.
Unmet Need. There exists in the art an unmet need for a modulator architecture that achieves improved velocity matching and impedance matching across the full length of a segmented traveling-wave electrode without sacrificing electro-optic modulation efficiency. In particular, there is a need for a segmented electrode design in which the transitions between adjacent electrode segments are engineered to suppress RF reflections and provide smooth, continuous impedance matching, thereby enabling the modulator to achieve electro-optic bandwidths in excess of 100 GHz per channel. The present invention addresses this unmet need.
Summary of the Invention
The present invention provides a multi-channel silicon-photonic Mach-Zehnder modulator with a segmented traveling-wave electrode architecture featuring a tapered impedance-matching configuration between adjacent electrode segments. The key differentiating feature of the present invention is that each pair of adjacent electrode segments is coupled through a tapered impedance-matching region that provides a smooth, continuous transition in the characteristic impedance of the electrode transmission line, thereby eliminating the abrupt impedance discontinuities that are characteristic of prior art uniform-segment designs.
In the tapered impedance-matching region, the geometry of the electrode—specifically, the width of the signal conductor and/or the gap between the signal and ground conductors—is gradually varied over a defined transition length to effect a continuous change in the characteristic impedance from the value at the end of one segment to the value at the beginning of the adjacent segment. The impedance profile through the tapered region may follow any of several well-known taper functions, including, but not limited to, the Klopfenstein taper, the Hecken taper, or an exponential taper, each of which is designed to minimize RF reflections over a broad frequency band.
This tapered impedance-matching feature enables several critical performance advantages over prior art segmented electrode designs:
(a) Enhanced velocity matching: The gradual impedance transition in the tapered region allows for precise compensation of velocity mismatch accumulation across segments, enabling the RF and optical signals to remain in phase over the full length of the modulator. This results in higher modulation efficiency and extended electro-optic bandwidth.
(b) Suppressed RF reflections: The continuous impedance taper eliminates the abrupt impedance discontinuities at segment boundaries, reducing RF return loss by more than 10 dB across the operating bandwidth compared to untapered, uniform-segment designs. This reduction in reflections translates directly to improved modulation bandwidth and reduced frequency-dependent ripple in the electro-optic response.
(c) Extended modulation bandwidth: Simulations and prototype measurements demonstrate that the tapered-segment architecture achieves 3-dB electro-optic bandwidths exceeding 100 GHz per channel, compared to approximately 75 GHz for comparable uniform-segment designs. This bandwidth is sufficient to support 200 Gbaud PAM-4 modulation with adequate margin for practical transceiver implementations.
(d) Reduced drive voltage: The improved modulation efficiency resulting from better velocity and impedance matching enables a lower half-wave voltage (Vπ), reducing the power consumption of the driver electronics and improving overall link budget.
(e) Scalable multi-channel integration: The modulator architecture supports multi-channel configurations, including four-channel (4×200 Gbaud) configurations for 800G transceivers and eight-channel (8×200 Gbaud) configurations for 1.6T transceivers, with effective channel isolation and minimal electrical and optical crosstalk.
(f) CMOS-compatible fabrication: The modulator, including the tapered impedance-matching regions, is fabricated on standard SOI wafers using CMOS-compatible processes, including deep ultraviolet (DUV) lithography for waveguide and electrode patterning, ion implantation for PN junction formation, and standard back-end-of-line (BEOL) metallization for electrode fabrication. The tapered geometry of the impedance-matching regions is defined lithographically in a single mask step, adding no additional process complexity.
Accordingly, the present invention provides, in one aspect, a multi-channel silicon-photonic Mach-Zehnder modulator comprising a plurality of Mach-Zehnder interferometer channels formed on a silicon-on-insulator substrate, each channel having segmented traveling-wave electrodes with tapered impedance-matching regions between adjacent segments. In another aspect, the invention provides a method of modulating an optical signal using such a modulator. In yet another aspect, the invention provides an optical transceiver module incorporating the multi-channel modulator PIC together with driver ICs and optical coupling interfaces.
Brief Description of the Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present invention and, together with the detailed description, serve to explain the principles and features of the invention. In the drawings:
Figure 1 is a schematic top-down view of a multi-channel silicon-photonic Mach-Zehnder modulator array showing the arrangement of multiple MZM channels on a silicon-on-insulator photonic integrated circuit, including optical input and output waveguides, multimode interference (MMI) couplers, phase shifter regions, and electrode contact pads.
Figure 2 is a detailed plan view of a single MZM channel showing the segmented traveling-wave electrode layout, including the individual electrode segments, the tapered impedance-matching regions between adjacent segments, the RF input and termination pads, and the optical waveguide arms of the Mach-Zehnder interferometer.
Figure 3 is a cross-sectional view taken along line III-III of Figure 2, through an electrode segment, showing the PN junction phase shifter embedded within the silicon rib waveguide, the buried oxide (Box) layer, the multi-layer electrode metallization including the signal and ground conductors, and the interlayer dielectric stack.
Figure 4A is a detailed plan view of the tapered impedance-matching region between a first electrode segment and a second electrode segment, showing the gradual geometric taper in electrode signal conductor width over the transition length.
Figure 4B is a detailed plan view of the tapered impedance-matching region of Figure 4A, showing the gradual geometric taper in the gap between the signal conductor and the ground conductors over the transition length.
Figure 4C is a perspective view of the tapered impedance-matching region of Figures 4A and 4B, illustrating the three-dimensional electrode geometry in the taper region and the continuous PN junction phase shifter extending through the taper.
Figure 5 is a graph of simulated RF characteristic impedance (in ohms) as a function of position along the electrode length (in micrometers), comparing the impedance profile of a uniform-segment (prior art) design with that of a tapered-segment (present invention) design. The uniform-segment design exhibits abrupt impedance steps at segment boundaries, while the tapered-segment design shows smooth, continuous impedance transitions.
Figure 6 is a graph of simulated electro-optic frequency response (S21, in dB) as a function of modulation frequency (in GHz), comparing the modulation bandwidth of a four-segment uniform-impedance design with that of a four-segment tapered-impedance design according to the present invention. The tapered design exhibits a 3-dB electro-optic bandwidth exceeding 110 GHz, compared to approximately 75 GHz for the uniform design.
Figure 7 is a fabrication process flow diagram illustrating the principal process steps for fabricating the segmented traveling-wave electrode structure with tapered impedance-matching regions on an SOI substrate, including waveguide patterning, PN junction formation, contact and via formation, and multi-layer electrode metallization.
Figure 8 is a measured eye diagram at 200 Gbaud PAM-4 for a prototype single-channel Mach-Zehnder modulator employing the four-segment tapered-impedance electrode architecture of the present invention, showing open eyes and acceptable transmitter-and-dispersion-penalty (TDECQ) performance.
Figure 9 is a multi-channel module packaging schematic showing the co-packaging of a four-channel MZM photonic integrated circuit with driver ICs, a thermal interface material, a heat sink, and optical fiber coupling structures, illustrating thermal management considerations for high-power-density multi-channel transceiver modules.
Figure 10 is a block diagram of a 1.6T optical transceiver module incorporating an eight-channel MZM photonic integrated circuit fabricated according to the present invention, together with a multi-channel laser source, driver ICs, a digital signal processor (DSP), and fiber-optic coupling interfaces.
Detailed Description of Preferred Embodiments
The following detailed description sets forth exemplary embodiments of the present invention with reference to the accompanying drawings. It will be understood that the following description is not intended to limit the scope of the invention to the particular embodiments described, but rather to enable any person skilled in the art to make and use the invention. Numerous modifications, equivalents, and variations will be apparent to those skilled in the art, and all such modifications, equivalents, and variations are intended to fall within the spirit and scope of the invention as defined by the appended claims.
Throughout the specification, reference numerals are used consistently to refer to like elements across the several drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. As used herein, the term "approximately" or "about" when used in conjunction with a numerical value means within ±10% of the stated value, unless otherwise specified.
1. Overall Modulator Architecture
Referring now to Figure 1, an exemplary multi-channel silicon-photonic Mach-Zehnder modulator array 100 according to the present invention is fabricated on a silicon-on-insulator (SOI) substrate 102. The SOI substrate 102 comprises a crystalline silicon device layer 104 having a thickness of approximately 220 nm, disposed on a buried oxide (Box) layer 106 having a thickness of approximately 2.0 µm, which in turn is disposed on a silicon handle wafer 108. This SOI material platform is widely available from commercial wafer suppliers and is compatible with standard CMOS foundry processing.
The modulator array 100 comprises a plurality of Mach-Zehnder interferometer (MZI) channels 110a, 110b, 110c, 110d (collectively, "MZI channels 110"), arranged in a parallel configuration on the PIC. In the embodiment of Figure 1, four MZI channels 110 are shown, corresponding to a four-channel (4×200 Gbaud PAM-4) configuration suitable for an 800G optical transceiver module. However, it will be appreciated that the present invention is not limited to four channels; embodiments with eight channels (for 1.6T transceivers), two channels, or other numbers of channels are also contemplated and fall within the scope of the invention.
Each MZI channel 110 comprises an input optical waveguide 112 that receives a continuous-wave (CW) optical signal from an external or co-packaged laser source 114. The input waveguide 112 feeds into a 1×2 optical splitter 116, which may be implemented as a multimode interference (MMI) coupler, a Y-branch splitter, or a directional coupler. The splitter 116 divides the input optical signal into two substantially equal portions, which are directed into a first waveguide arm 118a and a second waveguide arm 118b of the Mach-Zehnder interferometer.
Each waveguide arm 118a, 118b includes a phase shifter region 120a, 120b, respectively, in which the optical phase of the propagating optical mode is modulated in response to an applied RF electrical signal. The phase shifter regions 120a, 120b comprise reverse-biased PN junctions embedded within the silicon rib waveguide, as described in greater detail below with reference to Figure 3.
The modulator operates in a push-pull configuration, in which complementary RF drive signals are applied to the phase shifter regions 120a and 120b of each MZI channel 110, such that the optical phase in one arm increases while the optical phase in the other arm decreases by a substantially equal amount. This push-pull operation provides efficient amplitude modulation with reduced chirp, which is desirable for high-speed optical communication systems.
After traversing the phase shifter regions 120a, 120b, the optical signals in the two arms are recombined at a 2×1 optical combiner 122, which may also be implemented as an MMI coupler. The resulting modulated optical signal is output through an output optical waveguide 124 for coupling to an optical fiber via an edge coupler 126, a V-groove fiber array, a photonic wire bond, or a grating coupler, depending on the packaging configuration of the transceiver module.
The optical waveguides 112, 118a, 118b, and 124 are rib waveguides formed in the crystalline silicon device layer 104, with a rib height of approximately 220 nm, a slab height of approximately 90 nm, and a rib width of approximately 400–500 nm, designed to support a single transverse-electric (TE) polarization mode at the operating wavelength. The operating wavelength may be in the C-band (approximately 1530–1565 nm) or the O-band (approximately 1260–1360 nm), depending on the target transceiver application.
2. Segmented Traveling-Wave Electrode Design
Referring now to Figure 2, the traveling-wave electrode structure 200 associated with a single MZI channel 110 is described in greater detail. The electrode structure 200 comprises a plurality of electrode segments 202a, 202b, 202c, 202d (collectively, "electrode segments 202") arranged sequentially along the length of the phase shifter region 120 of the MZI channel 110. In the embodiment of Figure 2, four electrode segments 202 (N=4) are shown, but it will be appreciated that the number of segments N may be varied depending on the design requirements; embodiments with N=4, N=6, N=8, and N=10 segments per channel are specifically contemplated and described herein.
Each electrode segment 202 comprises a coplanar transmission line structure overlying a corresponding portion of the PN junction phase shifter region 120. In a preferred embodiment, the transmission line structure is a coplanar stripline (CPS) configuration, comprising a signal conductor 204 and a ground conductor 206 disposed on either side of the signal conductor 204, with the PN junction phase shifter region 120 positioned beneath the signal conductor 204. In an alternative embodiment, the transmission line structure may be a coplanar waveguide (CPW) configuration, comprising a central signal conductor 204 flanked by two ground conductors 206a, 206b.
The electrode metallization is formed using a multi-layer metal stack compatible with standard CMOS back-end-of-line (BEOL) processes. In one embodiment, the metal stack comprises an aluminum/copper (Al/Cu) alloy. In another preferred embodiment, the metal stack comprises copper (Cu) formed by a damascene process, which provides lower RF resistive losses at high frequencies due to the higher conductivity of copper compared to aluminum. The electrode metallization typically comprises two or more metal layers interconnected by vias, with the uppermost metal layer providing the primary signal and ground conductors of the coplanar transmission line, and lower metal layers providing interconnections to the PN junction contacts and routing for DC bias signals.
The length of each electrode segment 202 is selected to optimize the trade-off between modulation efficiency and RF propagation loss within each segment. In a preferred embodiment, each electrode segment 202 has a length in the range of approximately 200 µm to approximately 800 µm. The total active electrode length (the sum of the lengths of all segments) for each MZI channel 110 is in the range of approximately 2 mm to approximately 6 mm, depending on the number of segments and the required Vπ.
RF Signal distribution to the electrode segments 202 is accomplished through a distributed driver architecture, in which a plurality of individual driver cells 208a, 208b, 208c, 208d (collectively, "driver cells 208") are electrically coupled to corresponding electrode segments 202a, 202b, 202c, 202d, respectively. Each driver cell 208 may be an individual amplifier stage within a distributed amplifier, or a separate CMOS or BiCMOS driver IC bump-bonded or wire-bonded to the corresponding electrode segment contact pad 210. The distributed driver architecture allows the RF power to be applied incrementally along the length of the modulator, reducing the RF loss per segment and extending the overall modulation bandwidth.
At the downstream end of the electrode structure 200 (i.e., at the end of the last electrode segment 202d in the direction of RF wave propagation), a termination impedance 212 is provided to absorb the residual RF energy and prevent reflections from the electrode termination. The termination impedance 212 is designed to match the characteristic impedance of the last electrode segment 202d at the termination frequency band.
3. Tapered Impedance-Matching Feature
The tapered impedance-matching feature is the central inventive element of the present disclosure. Referring now to Figures 4A, 4B, and 4C, the tapered impedance-matching region 300 disposed between each pair of adjacent electrode segments 202 is described in detail.
3.1 Structure of the Tapered Impedance-Matching Region. Between each pair of adjacent electrode segments (e.g., between segment 202a and segment 202b), a tapered impedance-matching region 300 provides a smooth, continuous transition in the characteristic impedance of the coplanar transmission line. The taper is achieved by gradually varying one or more geometric parameters of the electrode structure over a defined transition length L_t.
In a first preferred embodiment, the taper is achieved by gradually varying the width Ws of the signal conductor 204. Referring to Figure 4A, the signal conductor width Ws transitions from a first width Ws1 at the end of the first electrode segment 202a to a second width Ws2 at the beginning of the second electrode segment 202b. The transition occurs smoothly and continuously over the transition length L_t, without any abrupt step or discontinuity in the conductor width.
In a second preferred embodiment, the taper is additionally or alternatively achieved by gradually varying the gap G between the signal conductor 204 and the adjacent ground conductor(s) 206. Referring to Figure 4B, the gap G transitions from a first gap G1 at the end of the first electrode segment 202a to a second gap G2 at the beginning of the second electrode segment 202b. The transition in gap width is smooth and continuous over the transition length L_t.
In a third preferred embodiment, both the signal conductor width Ws and the gap G are simultaneously varied over the transition length Lt to achieve the desired impedance taper profile while maintaining other desirable transmission line properties, such as a target effective dielectric constant for velocity matching.
The transition length Lt is selected to be sufficiently long to provide adequate suppression of RF reflections over the target operating bandwidth, while being sufficiently short to minimize the total electrode length and the associated RF propagation losses. In preferred embodiments, the transition length Lt is in the range of approximately 50 µm to approximately 200 µm. In a particularly preferred embodiment, the transition length L_t is approximately 100 µm, which provides an optimal balance between reflection suppression and total electrode length for operating frequencies up to approximately 120 GHz.
Referring to Figure 4C, the tapered impedance-matching region 300 is shown in perspective view, illustrating that the electrode geometry transitions smoothly in three dimensions. Importantly, the PN junction phase shifter 120 extends continuously through the tapered impedance-matching region 300, without interruption. This ensures that the optical mode continues to be modulated throughout the tapered region, maintaining the overall modulation efficiency of the device. The doping profile of the PN junction may be adjusted within the tapered region to compensate for any change in the overlap between the RF field and the optical mode resulting from the change in electrode geometry.
3.2 Impedance Taper Functions. The variation of the characteristic impedance Z(x) through the tapered impedance-matching region 300 as a function of position x along the electrode (where x=0 at the beginning of the taper and x=L_t at the end of the taper) may follow any of several taper functions known in the art of microwave engineering. The choice of taper function affects the frequency response of the reflection coefficient of the taper, and different taper functions may be selected depending on the specific performance requirements of the modulator.
Klopfenstein Taper: In a first preferred embodiment, the impedance taper follows a Klopfenstein function, which provides the shortest taper length for a given maximum passband ripple specification. The Klopfenstein taper is defined by:
ln Z(x) = ½ ln(Z₁Z₂) + (Γ₀ / cosh A) · A² · φ(2x/L_t − 1, A)
where Z₁ is the characteristic impedance at the beginning of the taper, Z₂ is the characteristic impedance at the end of the taper, Γ₀ = ½ ln(Z₂/Z₁) is the reflection coefficient at zero frequency, A is a design parameter that determines the passband ripple level, and φ is a modified Chebyshev function. For the present application, A is selected to provide a maximum reflection coefficient magnitude of less than −30 dB across the operating bandwidth of DC to 120 GHz.
Hecken Taper: In a second preferred embodiment, the impedance taper follows a Hecken function, which provides a broader bandwidth with a more gradual roll-off of the reflection coefficient at the band edges compared to the Klopfenstein taper. The Hecken taper is particularly advantageous when the modulator is required to operate over a very wide bandwidth with minimal ripple in the electro-optic frequency response.
Exponential Taper: In a third preferred embodiment, the impedance taper follows a simple exponential function:
Z(x) = Z₁ · exp(αx)
where α = (1/L_t) · ln(Z₂/Z₁) is the exponential taper constant. The exponential taper provides a simple, easily fabricated geometry that offers adequate reflection suppression for many practical applications, although its reflection performance at the band edges is generally inferior to that of the Klopfenstein or Hecken tapers.
In all of the above taper embodiments, the geometric parameters of the electrode (Signal conductor width, gap width, or both) are computed from the impedance taper function Z(x) using electromagnetic models of the coplanar transmission line, taking into account the specific dielectric environment of the SOI platform (including the buried oxide layer, interlayer dielectrics, and passivation layers). The computed geometric profiles are then transferred to the electrode mask layout for lithographic patterning.
3.3 Performance Improvement from Tapered Impedance Matching. Referring now to Figure 5, the simulated RF characteristic impedance is plotted as a function of position along the electrode length for both a prior art uniform-segment design (curve 502) and the tapered-segment design of the present invention (curve 504). In the uniform-segment design (curve 502), the impedance exhibits abrupt step discontinuities at each segment boundary, where the impedance changes instantaneously from the value of one segment to the value of the next segment. In the tapered-segment design (curve 504), the impedance transitions smoothly and continuously through the tapered impedance-matching regions, with no abrupt discontinuities.
The RF return loss (S11) of the tapered-segment design is improved by more than 10 dB across the operating bandwidth of DC to 100 GHz compared to the uniform-segment design. Specifically, the simulated RF return loss for the tapered design is less than −20 dB across DC to 100 GHz, compared to less than −12 dB for the uniform design. This improvement in return loss translates directly to a reduction in the RF energy reflected back toward the driver circuits, improving the power efficiency of the modulation and reducing the potential for driver instability.
Referring now to Figure 6, the simulated electro-optic frequency response (S21) is plotted for both the uniform-segment design (curve 602) and the tapered-segment design (curve 604). The tapered-segment design achieves a 3-dB electro-optic bandwidth of greater than 110 GHz, compared to approximately 75 GHz for the uniform-segment design. Moreover, the electro-optic frequency response of the tapered-segment design is substantially flatter (i.e., exhibits less frequency-dependent ripple) than that of the uniform-segment design, which is beneficial for achieving high signal quality at 200 Gbaud PAM-4 modulation.
The velocity matching between the RF traveling wave and the optical mode is also improved by the tapered impedance-matching regions. In the tapered design, the gradual impedance transition allows the effective RF phase velocity to be precisely controlled through the transition region, compensating for any velocity mismatch that accumulates across individual segments. This velocity-matching improvement is a key contributor to the extended electro-optic bandwidth of the tapered design.
4. Phase Shifter Design
Referring again to Figure 3, the PN junction phase shifter 120 is formed within the silicon rib waveguide 118 in each arm of the Mach-Zehnder interferometer. The phase shifter 120 comprises a lateral PN junction formed by selective ion implantation of p-type and n-type dopants into the silicon rib waveguide 118.
In a preferred embodiment, the p-type region 302 is formed on one side of the waveguide rib by implantation of boron (B) at a concentration of approximately 3×10¹⁷ cm⁻³ to approximately 1×10¹⁸ cm⁻³, and the n-type region 304 is formed on the opposite side of the rib by implantation of phosphorus (P) at a concentration of approximately 3×10¹⁷ cm⁻³ to approximately 1×10¹⁸ cm⁻³. The junction between the p-type and n-type regions is positioned at or near the center of the waveguide rib, where the optical mode intensity is highest, to maximize the overlap between the depletion region (which is modulated by the applied RF voltage) and the optical mode.
Highly doped p++ and n++ contact regions 306, 308 are formed outside the optical mode region, at the edges of the slab regions of the rib waveguide, by implantation of boron and phosphorus, respectively, at concentrations exceeding 1×10²⁰ cm⁻³. These highly doped contact regions provide low-resistance ohmic contacts to the metal electrode structure via tungsten (W) vias 310 that extend through the interlayer dielectric stack.
The PN junction phase shifter 120 is operated under reverse bias, with a DC bias voltage in the range of approximately −1 V to approximately −4 V applied between the p-type and n-type regions. The applied RF signal modulates the reverse bias voltage, causing the width of the depletion region to vary in time, which in turn modulates the free-carrier concentration within the waveguide and, via the plasma dispersion effect, modulates the effective refractive index of the optical mode.
The modulation efficiency of the phase shifter is characterized by the Vπ·L product, which represents the product of the half-wave voltage (the RF voltage required to produce a π-radian phase shift) and the active electrode length. In a preferred embodiment, the Vπ·L product is in the range of approximately 1.5 V·cm to approximately 2.5 V·cm, which represents a favorable trade-off between modulation efficiency and optical insertion loss.
Importantly, the PN junction phase shifter 120 extends continuously through the tapered impedance-matching regions 300 between adjacent electrode segments 202. This ensures that the optical mode is continuously modulated throughout the tapered region, and no "dead zones" of unmodulated waveguide are introduced. The doping profile within the tapered region may be optimized independently to account for any variation in the RF-optical overlap that results from the changing electrode geometry in the taper.
5. Multi-Channel Integration
Returning to Figure 1, the multi-channel integration of the modulator array 100 is described. In a first embodiment, the modulator array 100 comprises four MZI channels 110a–110d, providing a four-channel configuration suitable for 800G optical transceivers operating at an aggregate data rate of 4 × 200 Gbaud × 2 bits/symbol (PAM-4) = 1600 Gbit/s gross, or approximately 800 Gbit/s net after forward error correction (FEC) overhead.
In a second embodiment, the modulator array 100 comprises eight MZI channels 110a–110h, providing an eight-channel configuration suitable for 1.6T optical transceivers operating at an aggregate data rate of 8 × 200 Gbaud × 2 bits/symbol (PAM-4) = 3200 Gbit/s gross, or approximately 1600 Gbit/s net.
The MZI channels 110 are arranged in a parallel configuration on the PIC, with a channel-to-channel pitch (center-to-center spacing) in the range of approximately 200 µm to approximately 500 µm. The channel pitch is selected to balance the competing requirements of minimizing the overall PIC footprint (for higher integration density and lower cost) and maintaining adequate isolation between adjacent channels to prevent electrical and optical crosstalk.
Electrical crosstalk between adjacent channels is mitigated by several design features:
(a) Shared ground planes with isolation slots: The ground conductors 206 of the coplanar transmission lines of adjacent channels share a common ground plane, but isolation slots 402 are etched into the ground plane between adjacent channels to interrupt the flow of crosstalk currents. The isolation slots 402 have a width of approximately 5 µm to approximately 20 µm and extend along the full length of the phase shifter region.
(b) Deep-trench isolation: Deep isolation trenches 404 are formed in the silicon substrate between adjacent MZI channels 110, extending through the silicon device layer 104, through the box layer 106, and into the silicon handle wafer 108. These deep trenches interrupt the parasitic substrate coupling paths that can carry RF energy between adjacent channels.
(c) Electromagnetic shielding layers: Additional metal shielding layers 406 may be incorporated in the BEOL metal stack between the electrode layers of adjacent channels to provide additional electromagnetic isolation.
Optical crosstalk between adjacent channels is mitigated by ensuring adequate spatial separation between the optical waveguides of adjacent channels and by incorporating optical isolation structures, such as dummy waveguides or absorbing regions, between adjacent channel waveguides.
6. Simulation Results and Performance Data
The performance of the tapered-segment electrode architecture of the present invention has been evaluated through detailed electromagnetic and electro-optic simulations, as well as through measurements of prototype devices fabricated on 300 mm SOI wafers.
6.1 Simulated Electro-Optic Bandwidth. Referring to Figure 6, the electro-optic frequency response (S21) was simulated for a four-segment (N=4) MZM with tapered impedance-matching regions (curve 604, "tapered design") and for an equivalent four-segment MZM with uniform (untapered) segment boundaries (curve 602, "uniform design"). The simulation model included the full electromagnetic behavior of the coplanar transmission line (including conductor loss, dielectric loss, and radiation loss), the frequency-dependent PN junction capacitance, and the velocity mismatch between the RF and optical modes.
The simulation results demonstrate the following:
(a) The tapered design achieves a 3-dB electro-optic bandwidth of approximately 112 GHz, compared to approximately 75 GHz for the uniform design, representing an improvement of approximately 49%.
(b) The electro-optic frequency response of the tapered design exhibits less than ±0.5 dB of ripple across the band from DC to 80 GHz, compared to approximately ±1.5 dB of ripple for the uniform design. This reduced ripple translates to improved signal integrity at high symbol rates.
(c) At 100 GHz, the electro-optic response of the tapered design is only 2.1 dB below its low-frequency value, compared to 5.8 dB for the uniform design.
6.2 Simulated RF Return Loss. The simulated RF return loss (S11) for the tapered design is less than −20 dB across the entire operating bandwidth from DC to 100 GHz, compared to less than −12 dB for the uniform design. The improvement in return loss is most pronounced in the frequency range from 30 GHz to 100 GHz, where the impedance discontinuities at the segment boundaries of the uniform design generate strong reflections. In the tapered design, the gradual impedance transitions suppress these reflections, resulting in a smooth, low-reflection impedance profile along the full electrode length.
6.3 Simulated Drive Voltage. The simulated half-wave voltage (Vπ) for the tapered design is approximately 3.5 V at 50 GHz for the full electrode length (approximately 3.2 mm total active length across four segments), corresponding to a Vπ·L product of approximately 1.12 V·cm. This represents an improvement of approximately 15% compared to the uniform design (Vπ of approximately 4.1 V at 50 GHz for the same total electrode length), attributable to the improved RF-to-optical power transfer efficiency resulting from better impedance and velocity matching.
6.4 Eye Diagram Performance. Referring to Figure 8, a measured eye diagram at 200 Gbaud PAM-4 is shown for a prototype single-channel MZM employing the four-segment tapered-impedance electrode architecture. The prototype was fabricated on a 300 mm SOI wafer and tested using a commercial-grade arbitrary waveform generator (AWG) and high-speed sampling oscilloscope. The measured eye diagram exhibits clearly open eyes for all three PAM-4 eye openings, with a measured transmitter-and-dispersion-penalty (TDECQ) of approximately 2.3 dB, which is well within the performance requirements for 200 Gbaud PAM-4 transceiver applications. The inner and outer eye heights are substantially uniform, indicating good linearity of the modulator response.
7. Fabrication Process Overview
Referring now to Figure 7, the principal fabrication process steps for the segmented traveling-wave electrode structure with tapered impedance-matching regions on an SOI substrate are described. The process flow is compatible with standard CMOS foundry processes and can be implemented on 200 mm or 300 mm SOI wafers.