EXHIBIT C
UNITED STATES DISTRICT COURT EASTERN DISTRICT OF TEXAS MARSHALL DIVISION
OPTIWAVE SEMICONDUCTOR CORP., Plaintiff,
v.
LUMICORE TECHNOLOGIES, INC., Defendant.
Case No. 2:24-cv-00319-JRG
Before the Honorable James R. Gilstrap United States District Judge
EXHIBIT C TO ORIGINAL COMPLAINT
U.S. Patent No. 9,678,562 B2
"Method for Thermal Management of Photonic Integrated Circuits Using Embedded Micro-Channel Heat Sinks"
Issued June 13, 2017
Filed: April 22, 2024
Counsel of Record for Plaintiff Optiwave Semiconductor Corp.:
Alan Ngo (Responsible Partner) Cal. Bar No. 247891 Calderwood & Harkness LLP 350 South Grand Avenue, 48th Floor Los Angeles, CA 90071 Telephone: (213) 555-4200 Facsimile: (213) 555-4201
Email: ango@calderwoodharkness.com
Marcus Delgado (Billing Partner) Cal. Bar No. 263504 Calderwood & Harkness LLP 350 South Grand Avenue, 48th Floor Los Angeles, CA 90071 Telephone: (213) 555-4210
Email: mdelgado@calderwoodharkness.com
Wendy Schultz (Lead Associate) Cal. Bar No. 312877 Calderwood & Harkness LLP 350 South Grand Avenue, 48th Floor Los Angeles, CA 90071 Telephone: (213) 555-4225
Email: wschultz@calderwoodharkness.com
Omar Siddiqui (Working Associate) Cal. Bar No. 329146 Calderwood & Harkness LLP 350 South Grand Avenue, 48th Floor Los Angeles, CA 90071 Telephone: (213) 555-4233
Email: osiddiqui@calderwoodharkness.com
Local Counsel:
James "Jim" Callahan Tex. Bar No. 03614782 Whitmore & Callahan LLP 110 North College Avenue, Suite 800 Tyler, TX 75702 Telephone: (903) 555-8100 Facsimile: (903) 555-8101
Email: jcallahan@whitmorecallahan.com
CLERK'S CERTIFICATION
I, the undersigned Clerk of the United States District Court for the Eastern District of Texas, marshall Division, do hereby certify that the document attached hereto and made a part of this Exhibit C is a true and correct copy of United States Patent No. 9,678,562 B2, entitled "Method for Thermal Management of Photonic Integrated Circuits Using Embedded Micro-Channel Heat Sinks," as obtained from the records of the United States Patent and Trademark Office, Alexandria, Virginia.
This certified copy is provided for use as an exhibit in the civil proceedings captioned Optiwave Semiconductor Corp. v. Lumicore Technologies, Inc., Case No. 2:24-cv-00319-JRG, pending before this Court.
I further certify that I have compared the attached copy with the original patent document on file with the United States Patent and Trademark Office and that it is a complete and accurate reproduction of the same, including all claims, specifications, drawings, and bibliographic data as issued.
IN WITNESS WHEREOF, I have hereunto set my hand and affixed the seal of the United States District Court for the Eastern District of Texas, this 22nd day of April, 2024.
________________________________________
Deputy Clerk United States District Court Eastern District of Texas, marshall Division
[SEAL]
UNITED STATES PATENT
(54) METHOD FOR THERMAL MANAGEMENT OF PHOTONIC INTEGRATED CIRCUITS USING EMBEDDED MICRO-CHANNEL HEAT SINKS
(75) Inventors:
Dr. Henrik Vasquez, San Jose, CA (US) Dr. Mei-Ling Chow, Sunnyvale, CA (US) Dr. Arjun Deshmukh, Santa Clara, CA (US)
(73) Assignee:
Original Assignee: Solara Optics, Inc., San Jose, CA (US) Current Assignee: Optiwave Semiconductor Corp., Santa Clara, CA (US) — assigned via Asset Purchase Agreement dated June 15, 2018 (recorded assignment, Reel/Frame: 046218/0534)
(21) Application No.: 14/551,238
(22) Filed: November 22, 2014
(65) Prior Publication Data:
US 2015/0168247 A1 — Published June 18, 2015
(63) Related U.S. Application Data:
This application is the parent application in a patent family that includes U.S. Patent No. 10,234,847 B2 (the "'847 Patent"), entitled "Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss," filed September 14, 2016, issued March 19, 2019, which is a continuation-in-part of Application No. 14/551,238 (the present application). The '562 Patent and the '847 Patent share common subject matter relating to thermal management of photonic integrated circuits and are part of the same patent family.
(51) International Classification:
H01L 23/473 (2006.01) G02B 6/12 (2006.01) H01L 31/024 (2006.01)
(52) U.S. Classification:
257/714; 385/14; 165/80.4
(58) Field of Classification Search:
CPC: H01L 23/473; G02B 6/12; H05K 7/20 USPC: 257/714; 385/14; 165/80.4; 165/104.33; 257/712; 438/122 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
FOREIGN PATENT DOCUMENTS
OTHER PUBLICATIONS
Dr. Li Wei, "Thermal Solutions for PICs," Conference Paper, Optical Fiber Communication Conference and Exposition (OFC 2013), Paper OTh3G.5, Anaheim, CA, March 17–21, 2013 (cited by Examiner; also cited by Lumicore in invalidity contentions under 35 U.S.C. § 102).
Tuckerman, D.B. and Pease, R.F.W., "High-Performance Heat Sinking for VLSI," IEEE Electron Device Letters, Vol. EDL-2, No. 5, pp. 126–129, May 1981.
Kandlikar, S.G. and Grande, W.J., "Evolution of Microchannel Flow Passages — Thermohydraulic Performance and Fabrication Technology," Heat Transfer Engineering, Vol. 24, No. 1, pp. 3–17, 2003.
Qu, W. and Mudawar, I., "Experimental and Numerical Study of Pressure Drop and Heat Transfer in a Single-Phase Micro-Channel Heat Sink," International Journal of Heat and Mass Transfer, Vol. 45, No. 12, pp. 2549–2565, 2002.
Koo, J.M. et al., "Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures," Journal of Heat Transfer, Vol. 127, No. 1, pp. 49–58, January 2005.
Brunschwiler, T. et al., "Interlayer Cooling Potential in Vertically Integrated Packages," Microsystem Technologies, Vol. 15, pp. 57–74, 2009.
Kopp, C. et al., "Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 17, No. 3, pp. 498–509, May/June 2011.
Assefa, S. et al., "A 90nm CMOS Integrated Nano-Photonics Technology for 25Gbps WDM Optical Communications Applications," Technical Digest, International Electron Devices Meeting (IEDM 2012), pp. 33.8.1–33.8.3, December 2012.
Zhang, L. et al., "Microfluidic Cooling of Integrated Circuits," Proceedings of SPIE, Vol. 8615, pp. 861502-1 to 861502-8, 2013.
Sun, C. et al., "Single-Chip Microprocessor that Communicates Directly Using Light," Nature, Vol. 528, pp. 534–538, December 2015 (post-filing date reference cited for background context only).
(74) Attorney, Agent, or Firm:
Cascade IP Advisors, LLC, Arlington, VA Lead Prosecution Attorney: Dr. Martin Chu, Reg. No. 62,418
(72) Primary Examiner: Daniel R. Fitzpatrick
(72) Assistant Examiner: Sarah L. Morton
ABSTRACT.
A method and apparatus for thermal management of photonic integrated circuits (PICs) using embedded micro-channel heat sinks. The invention provides a heat-dissipating structure containing channels with a hydraulic diameter of less than 1 mm, formed within or adjacent to the substrate of a photonic integrated circuit. The micro-channel heat sink is configured to remove excess heat generated by active optical components (lasers, modulators, photodetectors) integrated on the PIC, thereby maintaining stable operating temperatures and ensuring reliable performance of the photonic circuit. The method includes steps of forming the micro-channels using MEMS-compatible etching processes, integrating coolant distribution manifolds, and bonding the micro-channel layer to the PIC substrate. The thermal management approach achieves a thermal resistance reduction of at least 40% compared to conventional heat-spreading solutions for photonic integrated circuits operating at data rates of 100 Gb/s and above.
BRIEF DESCRIPTION OF THE DRAWINGS
The following drawings are included as part of the patent specification and are incorporated herein by reference. Each drawing is identified below with a brief description of its content. All drawings are schematic in nature and are not drawn to scale unless otherwise indicated.
FIG. 1 is a cross-sectional view of a photonic integrated circuit (PIC) with the embedded micro-channel heat sink structure of the present invention, showing the silicon substrate, optical waveguide layer, active components (including a laser diode, optical modulator, and photodetector), and the micro-channel cooling layer positioned beneath the PIC substrate.
FIG. 2 is a top-down view of the micro-channel layout according to a preferred embodiment of the present invention, illustrating the branching network of channels with specified hydraulic diameters, the primary manifold channels, secondary distribution channels, and the coolant inlet and outlet manifold ports located at opposing edges of the heat-sink substrate.
FIG. 3 is a detailed cross-section of a single micro-channel according to the present invention, showing channel dimensions including width, depth, and wall thickness, the direction of coolant flow through the channel, and the thermal interface between the channel wall and the PIC substrate, including the thermal interface material layer.
FIG. 4 is a schematic diagram of the coolant distribution system according to a preferred embodiment of the present invention, including the micro-pump, coolant reservoir, heat exchanger (radiator), temperature sensors, and manifold connections to the micro-channel array, with arrows indicating the direction of coolant flow through the closed-loop system.
FIG. 5 shows thermal simulation results comparing temperature distribution across the PIC surface in two configurations: (a) without a micro-channel heat sink, showing elevated hotspot temperatures in excess of 85°C concentrated around active laser components; and (b) with the embedded micro-channel heat sink of the present invention, demonstrating a substantially uniform temperature distribution with a maximum hotspot temperature of approximately 52°C.
FIG. 6 is a process flow diagram illustrating the fabrication steps for the micro-channel heat sink according to the present invention, including the following sequential steps: (1) substrate preparation, (2) deep reactive ion etching (DRIE) of channels, (3) surface passivation with thermal oxide or silicon nitride, (4) manifold integration and port formation, and (5) wafer bonding of the micro-channel substrate to the PIC substrate.
FIG. 7 is a graph of thermal resistance (in K/W) versus coolant flow rate (in mL/min) for various micro-channel hydraulic diameters, including 50 µm, 100 µm, 200 µm, and 500 µm, showing the relationship between channel geometry, flow rate, and thermal performance for the micro-channel heat sink of the present invention.
FIG. 8 is an exploded view of a multi-layer PIC package incorporating the micro-channel heat sink of the present invention, showing the spatial relationship among the optical input/output (I/O) interface, electrical interconnection layers, the PIC die, the micro-channel cooling layer, and the package substrate.
FIG. 9 is a cross-sectional view of an alternative embodiment of the present invention, showing micro-channels formed directly in the PIC silicon substrate using through-silicon via (TSV) compatible etching processes, wherein the micro-channels are etched into the backside of the PIC die and sealed with a bonded cap layer.
FIG. 10 is a graph of optical output power stability (in dBm) versus operating time (in hours) over a 1000-hour continuous operation test, comparing the performance of photonic integrated circuit devices with the micro-channel thermal management system of the present invention (showing ±0.3 dB output power variation) against devices employing a conventional planar heat spreader (showing ±1.2 dB output power variation).
SPECIFICATION
FIELD OF THE INVENTION
The present invention relates generally to thermal management of photonic integrated circuits, and more particularly, to methods and structures for embedding micro-channel heat sinks within or adjacent to photonic integrated circuit substrates to dissipate heat generated by active optical components operating at high data rates. The invention is particularly applicable to silicon photonic transceivers and related devices operating at data rates of 100 Gb/s and above, as employed in data-center and telecommunications applications where high-density optical interconnects demand efficient and compact thermal management solutions.
BACKGROUND OF THE INVENTION
The rapid growth of cloud computing, streaming media, artificial intelligence workloads, and Internet-of-Things connectivity has driven an exponential increase in demand for high-bandwidth optical interconnects within hyperscale data centers and metropolitan-area telecommunications networks. To meet this demand, the photonics industry has increasingly turned to photonic integrated circuits (PICs) — monolithically integrated optical devices fabricated on semiconductor substrates — as a means of achieving high data throughput in compact, energy-efficient packages. Silicon photonics, in particular, has emerged as a leading platform for such integration, leveraging the mature complementary metal-oxide-semiconductor (CMOS) fabrication infrastructure to produce complex optical systems on a single chip.
A typical silicon photonic transceiver PIC may integrate multiple active optical components on a single die, including semiconductor lasers or laser drivers, high-speed optical modulators (such as Mach-Zehnder interferometers or ring resonators), photodetectors (germanium-on-silicon photodiodes), wavelength-division multiplexing (WDM) multiplexers and demultiplexers, and associated electronic driver and transimpedance amplifier (TIA) circuits. As integration density increases — driven by the need to support data rates of 100 Gb/s, 400 Gb/s, and beyond on a single module — the aggregate power dissipation of these active components rises correspondingly. Semiconductor lasers alone may dissipate several watts of thermal energy per chip, and when combined with the power consumption of high-speed modulators, drivers, and associated electronics, the total heat load on a modern PIC can exceed 10 watts in a package footprint of only a few square centimeters.
This thermal challenge is particularly acute for photonic integrated circuits because the performance of active optical components is highly sensitive to temperature. Semiconductor lasers exhibit wavelength drift, threshold current increase, and reduced efficiency as junction temperature rises. Optical modulators based on the thermo-optic or electro-optic effect experience changes in operating point and extinction ratio with temperature fluctuations. Wavelength multiplexers and demultiplexers relying on resonant structures (such as arrayed waveguide gratings or ring resonators) are especially vulnerable to thermal drift, as even small temperature changes (on the order of fractions of a degree Celsius) can shift the passband wavelengths and degrade channel isolation. Accordingly, effective thermal management is essential not only for device reliability and longevity but also for maintaining the optical performance specifications required for high-data-rate communications.
Conventional thermal management approaches for semiconductor devices include passive heat spreaders (typically copper or aluminum alloy plates bonded to the back side of the die), thermoelectric coolers (TECs), and external finned heat sinks with forced-air cooling. While these approaches have been widely adopted in electronic IC packaging, they face significant limitations when applied to photonic integrated circuits. Passive heat spreaders provide only modest thermal resistance reduction and are insufficient for the high heat flux densities (exceeding 100 W/cm² in localized hotspots) encountered in advanced PICs. Thermoelectric coolers consume substantial electrical power, add significant package volume, and introduce vibration that can affect optical alignment. External heat sinks with forced-air cooling are effective for moderate heat loads but are impractical for the compact, high-density module form factors (such as QSFP-DD and OSFP) required by data-center interconnect standards.
Micro-channel cooling technology, originally demonstrated by Tuckerman and Pease in 1981 for very-large-scale integration (VLSI) electronic circuits, offers the potential for dramatically higher heat transfer coefficients compared to conventional approaches. By forcing coolant through an array of narrow channels with hydraulic diameters on the order of tens to hundreds of micrometers, micro-channel heat sinks can achieve thermal resistances an order of magnitude lower than those of planar heat spreaders. The small channel dimensions promote laminar flow with high surface-area-to-volume ratios, enabling efficient heat removal in a compact structure. Micro-channel cooling has been studied extensively for electronic chip cooling and has been implemented in some high-performance computing and power electronics applications.
However, at the time of the present invention, micro-channel cooling technology had not been effectively adapted to photonic integrated circuits. The unique constraints of photonic IC fabrication present several challenges not encountered in electronic IC cooling: (1) optical waveguides and resonant structures are sensitive to mechanical stress and strain, which can alter the effective refractive index and degrade optical performance — bonding or forming cooling structures adjacent to the PIC substrate must therefore be accomplished without introducing excessive stress; (2) the fabrication processes used for micro-channel formation must be compatible with the materials and process temperatures used in silicon photonics fabrication, particularly avoiding temperatures that could damage or shift the optical properties of waveguides and active components; (3) the micro-channel cooling structure must not interfere with the optical input/output coupling (whether via fiber attachment, grating couplers, or edge couplers) or with the electrical interconnections on the PIC; and (4) the coolant must be compatible with the photonic device materials and packaging, presenting no risk of corrosion, contamination, or optical surface degradation.
Thus, a need existed for a thermal management solution that effectively combined the high heat-transfer performance of micro-channel cooling with the specific fabrication and performance constraints of photonic integrated circuits — a solution that could be manufactured using MEMS-compatible and CMOS-compatible processes, integrated seamlessly with PIC substrates, and deployed in the compact module form factors demanded by the data-center and telecommunications industries.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by providing a method and apparatus for thermal management of photonic integrated circuits using embedded micro-channel heat sinks. In accordance with the invention, a micro-channel heat sink — defined herein as a heat-dissipating structure containing channels with a hydraulic diameter of less than 1 mm — is formed in a substrate and integrated with or bonded to a photonic integrated circuit substrate to provide efficient heat removal from active optical components on the PIC.
The micro-channels are formed using MEMS-compatible etching processes, particularly deep reactive ion etching (DRIE), which enables the creation of high-aspect-ratio channels with precise dimensional control. The channels may be formed in a separate heat-sink substrate (e.g., silicon or glass) that is subsequently bonded to the PIC substrate, or alternatively, the channels may be etched directly into the backside of the PIC silicon substrate itself. In either configuration, the micro-channel heat sink is thermally coupled to the PIC substrate such that heat generated by the active optical components on the front side of the PIC is conducted through the substrate and removed by coolant flowing through the micro-channels on the back side.
The method of the present invention achieves a thermal resistance reduction of at least 40% compared to conventional planar heat-spreading solutions for photonic integrated circuits operating at data rates of 100 Gb/s and above. In preferred embodiments, the micro-channel heat sink reduces the thermal resistance between the active optical components and an external heat exchange surface from approximately 0.25 K/W (using a conventional copper heat spreader) to approximately 0.15 K/W, resulting in hotspot temperature reductions of more than 30°C under typical operating conditions.
Key advantages of the present invention include: (1) compatibility with standard silicon photonics fabrication processes, including CMOS-compatible temperatures and materials; (2) scalability to large wafer sizes and high-volume manufacturing; (3) minimal impact on optical alignment and waveguide performance due to the use of low-stress bonding techniques and careful thermal interface design; (4) versatility in coolant selection, including both liquid coolants (deionized water, fluorocarbon-based dielectric fluids) and phase-change working fluids for passive operation; and (5) applicability to a wide range of PIC architectures, including silicon photonics transceivers operating at data rates of 400 Gb/s and beyond.
The invention further encompasses passive micro-channel heat sink embodiments in which the micro-channels are filled with a phase-change working fluid and operate on capillary-driven or heat-pipe principles, requiring no external pump or active coolant circulation system. Such passive embodiments are particularly suitable for lower-power PIC applications or environments where active cooling infrastructure is unavailable, while still providing significant thermal management improvement over conventional planar heat spreaders.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications, and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.
Embodiment 1: Bonded Micro-Channel Layer. Referring to FIGS. 1 through 4 and 8, a first preferred embodiment of the present invention is described. In this embodiment, a separate micro-channel heat-sink substrate 100 is fabricated from a silicon wafer or, alternatively, from a borosilicate glass substrate. The micro-channel heat-sink substrate 100 is a distinct component from the photonic integrated circuit die 200, and the two are bonded together during the packaging process.
The micro-channels 110 are formed in the heat-sink substrate 100 using deep reactive ion etching (DRIE), also known as the Bosch process. The DRIE process produces channels with substantially vertical sidewalls and high aspect ratios, enabling precise control over channel geometry. In the preferred embodiment, the micro-channels 110 have the following dimensional ranges:
• Channel width: 50 µm to 500 µm
• Channel depth: 100 µm to 800 µm
• Wall thickness between adjacent channels: 20 µm to 100 µm
• Hydraulic diameter: approximately 50 µm to 500 µm (all less than 1 mm)
• Channel length: 5 mm to 20 mm, depending on the PIC die dimensions
The hydraulic diameter Dh of a rectangular channel is defined as Dh = 4A/P, where A is the cross-sectional area of the channel and P is the wetted perimeter. For the rectangular channel geometries employed in the present invention, the hydraulic diameter ranges from approximately 50 µm (for narrow, deep channels) to approximately 500 µm (for wider, shallower channels), all of which are well below the 1 mm threshold that defines micro-channels in the context of the present invention.
The micro-channels 110 are arranged in a branching network configuration as illustrated in FIG. 2. A primary manifold channel 120 extends along one edge of the heat-sink substrate 100 and distributes coolant to a plurality of secondary distribution channels 130 that extend in a parallel or branching pattern across the substrate surface. A corresponding primary manifold channel 140 on the opposite edge of the substrate collects the coolant after it has traversed the distribution channels. Coolant inlet port 125 and coolant outlet port 145 are formed at the ends of the primary manifold channels 120 and 140, respectively, to connect to an external coolant circulation system.
The coolant employed in the preferred embodiment is deionized water, which provides excellent thermal conductivity and heat capacity. In applications where electrical isolation or chemical compatibility is a concern, a fluorocarbon-based dielectric fluid (such as Ridgeline Group FC-72 or FC-77) may be substituted. The dielectric fluid provides the additional advantage of electrical insulation, reducing the risk of short circuits in the event of a coolant leak in proximity to the PIC electrical interconnections.
As shown in FIG. 1, the micro-channel heat-sink substrate 100 is bonded to the underside (back side) of the photonic integrated circuit die 200 using a bonding process selected from thermocompression bonding, anodic bonding, or adhesive bonding. Thermocompression bonding is preferred for silicon-to-silicon bonding, as it provides a hermetic seal and excellent thermal contact. The thermocompression bonding process is conducted at temperatures below 300°C to avoid thermal damage to the optical waveguides and active components on the front side of the PIC die 200. A thin thermal interface material (TIM) layer 150, such as an indium-based solder layer or a thermal epoxy, may be disposed between the heat-sink substrate 100 and the PIC die 200 to fill microscopic surface irregularities and reduce interfacial thermal resistance.
The external coolant circulation system (illustrated schematically in FIG. 4) includes a micro-pump 300, a coolant reservoir 310, a heat exchanger 320 (which dissipates the collected heat to the ambient environment), temperature sensors 330, and fluid interconnections to the inlet and outlet ports 125 and 145 of the micro-channel substrate. The micro-pump 300 provides a controlled coolant flow rate in the range of 10 mL/min to 200 mL/min, depending on the thermal load and channel geometry.
Embodiment 2: Directly Etched Micro-Channels in PIC Substrate. Referring to FIG. 9, an alternative embodiment of the present invention is described in which the micro-channels are etched directly into the backside of the photonic integrated circuit silicon substrate 200, rather than being formed in a separate heat-sink substrate. This approach eliminates the bonding step and reduces the overall package thickness, which is advantageous for compact module form factors.
In this embodiment, the PIC die 200 is fabricated on a silicon-on-insulator (SOI) wafer. The active optical components and waveguides are formed on the front side of the SOI wafer using standard silicon photonics fabrication processes. After front-side processing is complete, the wafer is thinned from the back side to a thickness of approximately 200 µm to 500 µm. Micro-channels 210 are then etched into the thinned back side of the wafer using DRIE. The channel dimensions and hydraulic diameters are similar to those described in Embodiment 1 above.
The DRIE process for back-side etching is designed to be compatible with through-silicon via (TSV) fabrication processes, which are well established in the semiconductor industry for three-dimensional IC integration. The channel depth is controlled such that the etching stops at a safe distance (at least 50 µm) from the buried oxide (Box) layer of the SOI substrate, ensuring that the optical waveguide layer on the front side is not compromised.
After micro-channel etching, the channel surfaces are passivated (as described below in the fabrication process section) and the open back side of the micro-channels is sealed by bonding a cap layer 220 — a planar silicon or glass wafer — to the back side of the PIC die. Coolant inlet and outlet ports are formed through the cap layer 220 or through the edges of the PIC die.
This embodiment offers several advantages over the bonded micro-channel layer of Embodiment 1: (1) the elimination of the separate heat-sink substrate reduces material cost and simplifies the assembly process; (2) the direct thermal path from the active components through the PIC substrate to the micro-channels minimizes interfacial thermal resistance; and (3) the TSV-compatible process flow enables integration with other three-dimensional packaging technologies.
Embodiment 3: Passive Micro-Channel Heat Sink (No Pumped Coolant). In a further alternative embodiment of the present invention, the micro-channels are utilized in a passive cooling configuration that does not require an external pump or active coolant circulation system. In this embodiment, the micro-channels are formed as described in Embodiment 1 or Embodiment 2, but instead of being connected to an external coolant loop, the channels are charged with a phase-change working fluid (such as methanol, acetone, or a fluorocarbon) and sealed.
The passive micro-channel heat sink operates on principles analogous to a micro-heat-pipe. The working fluid in the micro-channels near the heat source (i.e., adjacent to the active optical components on the PIC) absorbs heat and evaporates. The vapor travels through the channels to a cooler region of the substrate, where it condenses and releases the absorbed heat. The condensed liquid returns to the heat source region by capillary action along the channel walls, completing the cycle without the need for a pump.
To enhance capillary-driven liquid return, the channel surfaces in this embodiment may be textured or roughened during the DRIE process, or a wicking structure (such as a porous silicon layer or a sintered metal wick) may be formed on the channel walls. The hydraulic diameters of the channels in this embodiment are selected to promote capillary-dominated flow, typically in the range of 50 µm to 300 µm.
The passive micro-channel heat sink embodiment is particularly suitable for lower-power PIC applications (e.g., receiver-only PICs or PICs with total power dissipation below 5 W) or for deployments in environments where active cooling infrastructure (pumps, reservoirs, external plumbing) is unavailable or impractical. While the thermal performance of the passive embodiment is somewhat lower than that of the actively cooled embodiments, it still provides a significant improvement over conventional planar heat spreaders and satisfies the definition of a "micro-channel heat sink" as used herein — namely, a heat-dissipating structure containing channels with a hydraulic diameter of less than 1 mm.
Fabrication Process. Referring to FIG. 6, the fabrication process for the micro-channel heat sink of the present invention is described in detail. The process comprises the following steps:
Step 1 — Substrate Preparation. A silicon wafer (or, alternatively, a borosilicate glass substrate) is cleaned using standard semiconductor cleaning protocols (e.g., RCA clean) to remove surface contaminants. The wafer thickness is selected based on the desired channel depth and the mechanical strength requirements of the heat-sink substrate. For a bonded micro-channel layer (Embodiment 1), a standard 500 µm to 700 µm thick silicon wafer is used. For directly etched channels (Embodiment 2), the PIC wafer is thinned as described above prior to channel etching.
Step 2 — Photolithographic Patterning. A photolithographic mask is applied to the substrate surface, defining the micro-channel layout, including the primary manifold channels, secondary distribution channels, and manifold ports. The photolithographic process uses standard photoresist materials (e.g., AZ 4620 thick photoresist) and contact or projection lithography tools. The mask design corresponds to the branching network configuration illustrated in FIG. 2, with channel widths, spacings, and manifold dimensions as specified for the particular embodiment.
Step 3 — Deep Reactive Ion Etching (DRIE). The patterned substrate is etched using a DRIE process (Bosch process) to form the micro-channels to the specified depth. The DRIE process alternates between etching cycles (using SF₆ plasma) and passivation cycles (using C₄F₈ plasma) to achieve substantially vertical sidewalls with scalloping depths of less than 0.5 µm. The etch rate is typically 5 µm/min to 15 µm/min, depending on channel width and aspect ratio. The process produces channels with aspect ratios (depth to width) of at least 5:1, and in some configurations up to 20:1.
Step 4 — Surface Passivation. After DRIE, the inner surfaces of the micro-channels are passivated to prevent chemical interaction between the coolant and the substrate material, to improve surface wettability, and to enhance thermal conductivity at the solid-fluid interface. Passivation is accomplished by forming a thin thermal oxide layer (SiO₂, thickness 100 nm to 500 nm) using dry thermal oxidation or, alternatively, by depositing a silicon nitride (Si₃N₄) layer using low-pressure chemical vapor deposition (LPCVD). The choice of passivation material depends on the coolant chemistry and the required surface properties.
Step 5 — Manifold Formation. Coolant inlet and outlet manifold ports are formed in the heat-sink substrate by through-wafer etching (using DRIE or laser drilling) at the designated locations. The manifold ports provide fluidic connections between the micro-channel array and the external coolant circulation system. In some embodiments, the manifold ports are formed on the edges of the substrate rather than through the wafer thickness, depending on the package design.
Step 6 — Wafer Bonding. The micro-channel heat-sink substrate is bonded to the PIC substrate (or, in Embodiment 2, the back side of the PIC die is sealed with a cap layer). The bonding process is selected from the following options:
(a) Thermocompression bonding: The two substrates are brought into contact under pressure (1 MPa to 10 MPa) at a temperature of 200°C to 300°C, causing interdiffusion and bonding at the interface. This process is preferred for silicon-to-silicon bonding and provides a hermetic seal.
(b) Anodic bonding: Used when one substrate is silicon and the other is borosilicate glass. The substrates are brought into contact at 300°C to 450°C with an applied voltage of 500 V to 1000 V across the interface, creating an electrostatic bond.
(c) Adhesive bonding: A thin layer of thermosetting adhesive (e.g., benzocyclobutene (BCB) or SU-8 epoxy) is applied to one or both bonding surfaces, and the substrates are brought into contact and cured at temperatures below 250°C. Adhesive bonding provides flexibility in material selection and is suitable for heterogeneous integration.
In all cases, the bonding temperature is maintained below 300°C to preserve the integrity of the optical waveguides and active components on the PIC die.
Step 7 — External System Connection. For active cooling embodiments (Embodiments 1 and 2), the coolant inlet and outlet manifold ports are connected to the external coolant circulation system using micro-fluidic connectors, O-ring sealed fittings, or adhesive-bonded tubing. For passive cooling embodiments (Embodiment 3), the micro-channels are charged with the phase-change working fluid through the manifold ports, and the ports are then hermetically sealed.
Step 8 — Packaging and Testing. The assembled PIC with integrated micro-channel heat sink is packaged in the appropriate module form factor (e.g., QSFP-DD, OSFP, or custom package) and tested for thermal performance, optical performance, and fluidic integrity. Thermal testing includes measurement of thermal resistance, hotspot temperature mapping using infrared thermography, and coolant flow rate characterization. Optical testing includes verification of laser wavelength stability, modulator extinction ratio, and photodetector responsivity across the operating temperature range.
Performance Data. The thermal performance of the micro-channel heat sink of the present invention has been evaluated through both thermal simulation (finite-element analysis) and experimental measurement on prototype devices. The key performance metrics are summarized below.
Thermal Resistance. For a photonic integrated circuit with a total power dissipation of 10 W and a die area of 5 mm × 10 mm, the micro-channel heat sink of the present invention achieves a thermal resistance of 0.15 K/W between the active component junction and the coolant, compared to 0.25 K/W for a conventional copper heat spreader of equivalent footprint area. This represents a thermal resistance reduction of 40%, meeting the performance objective of the invention. As shown in FIG. 7, the thermal resistance decreases with increasing coolant flow rate and with decreasing micro-channel hydraulic diameter. For channels with a hydraulic diameter of 100 µm and a coolant flow rate of 100 mL/min, the thermal resistance is further reduced to 0.10 K/W, representing a 60% improvement over the conventional heat spreader.
Hotspot Temperature Reduction. Referring to the thermal simulation results of FIG. 5, the maximum hotspot temperature on the PIC surface under a full 10 W load is reduced from 85°C (without micro-channel heat sink) to 52°C (with the embedded micro-channel heat sink of the present invention), a reduction of 33°C. The temperature distribution is also substantially more uniform with the micro-channel heat sink, with a temperature variation across the PIC surface of less than 5°C, compared to more than 20°C without the heat sink.
Optical Output Power Stability. Referring to FIG. 10, the optical output power of a 100 Gb/s silicon photonic transceiver PIC equipped with the micro-channel heat sink of the present invention was measured continuously over a 1000-hour accelerated life test. The output power variation was ±0.3 dB, well within the ±1.0 dB specification required for data-center interconnect applications. In comparison, an identical PIC equipped with a conventional copper heat spreader exhibited output power variation of ±1.2 dB over the same test duration, exceeding the specification limit.
Wavelength Compatibility. The micro-channel heat sink structure and bonding process of the present invention were confirmed to have no measurable impact on the optical performance of PIC waveguides and components operating at wavelengths of 1310 nm and 1550 nm. Insertion loss measurements showed no increase attributable to the thermal management structure, and waveguide propagation loss remained unchanged within measurement uncertainty (±0.05 dB/cm) before and after integration of the micro-channel heat sink.
RELATIONSHIP TO OTHER APPLICATIONS IN THE PATENT FAMILY
The present application (Application No. 14/551,238, which matured into U.S. Patent No. 9,678,562 B2) is the parent application in a patent family. A continuation-in-part application, Application No. 15/265,491, was filed on September 14, 2016, claiming priority to the present application. That continuation-in-part application matured into U.S. Patent No. 10,234,847 B2, entitled "Multi-Channel Silicon Photonic Waveguide Multiplexer with Low Insertion Loss," issued on March 19, 2019, and currently assigned to Optiwave Semiconductor Corp.
The '847 Patent extended the thermal management concepts disclosed in the present invention to waveguide multiplexer structures specifically, addressing the particular thermal sensitivity of arrayed waveguide grating (AWG) and ring-resonator-based wavelength multiplexer/demultiplexer components. The '847 Patent incorporates the micro-channel heat sink technology of the present invention as an integral part of a thermally stabilized multiplexer architecture and includes additional subject matter directed to low-insertion-loss waveguide designs not disclosed in the present application.
The present application and the '847 Patent share common inventors (Dr. Henrik Vasquez and Dr. Mei-Ling Chow) and a common original assignee (Solara Optics, Inc.).
CLAIMS
What is claimed is:
1. A method for thermal management of a photonic integrated circuit, comprising:
(a) forming a plurality of micro-channels in a substrate, each micro-channel having a hydraulic diameter of less than 1 mm;
(b) positioning the substrate with the plurality of micro-channels adjacent to a photonic integrated circuit substrate having at least one active optical component formed thereon;
(c) thermally coupling the micro-channel substrate to the photonic integrated circuit substrate; and
(d) circulating a coolant through the plurality of micro-channels to dissipate heat generated by the at least one active optical component.
2. The method of claim 1, wherein the hydraulic diameter of each micro-channel is in the range of 50 µm to 500 µm.
3. The method of claim 1, wherein the coolant comprises deionized water or a fluorocarbon-based dielectric fluid.
4. The method of claim 1, wherein thermally coupling comprises bonding the micro-channel substrate to the photonic integrated circuit substrate using thermocompression bonding, anodic bonding, or adhesive bonding.
5. The method of claim 1, wherein the photonic integrated circuit comprises a silicon photonics transceiver operating at a data rate of at least 100 Gb/s.
6. An apparatus for thermal management of a photonic integrated circuit, comprising:
(a) a photonic integrated circuit substrate having at least one active optical component;
(b) a micro-channel heat sink comprising a plurality of channels formed in a heat-sink substrate, each channel having a hydraulic diameter of less than 1 mm, the micro-channel heat sink thermally coupled to the photonic integrated circuit substrate;
(c) a coolant distribution manifold fluidically connected to the plurality of channels; and
(d) wherein the micro-channel heat sink reduces thermal resistance between the at least one active optical component and an external heat exchange surface by at least 40% relative to a planar heat spreader of equivalent footprint area.
7. The apparatus of claim 6, wherein the photonic integrated circuit substrate comprises a silicon-on-insulator (SOI) wafer.
8. The apparatus of claim 6, wherein the at least one active optical component comprises one or more of: a laser, an optical modulator, a photodetector, and a wavelength multiplexer.
9. The apparatus of claim 6, further comprising a thermal interface material disposed between the micro-channel heat sink and the photonic integrated circuit substrate.
10. The apparatus of claim 6, wherein the plurality of channels are arranged in a branching network configuration with a primary manifold channel and a plurality of secondary distribution channels.
11. A method of fabricating an embedded micro-channel heat sink for a photonic integrated circuit, comprising:
(a) providing a silicon substrate;
(b) patterning a photolithographic mask on the silicon substrate defining a micro-channel layout;
(c) etching the silicon substrate through the photolithographic mask using deep reactive ion etching to form a plurality of micro-channels having hydraulic diameters in the range of 10 µm to 900 µm;
(d) passivating inner surfaces of the plurality of micro-channels;
(e) forming coolant inlet and outlet manifold ports in the silicon substrate;
(f) bonding the silicon substrate with the plurality of micro-channels to a backside surface of a photonic integrated circuit die; and
(g) connecting the coolant inlet and outlet manifold ports to an external coolant circulation system.
12. The method of claim 11, wherein the deep reactive ion etching produces channels with an aspect ratio of depth to width of at least 5:1.
13. The method of claim 11, wherein passivating comprises forming a thermal oxide layer or a silicon nitride layer on the inner surfaces of the micro-channels.
14. The method of claim 11, wherein bonding comprises thermocompression bonding at a temperature below 300°C to preserve optical waveguide integrity on the photonic integrated circuit die.
ASSERTED CLAIMS SUMMARY
The following summary is provided for the convenience of the Court and the parties. It does not form part of the patent specification.
In the Original Complaint filed in Optiwave Semiconductor Corp. v. Lumicore Technologies, Inc., Case No. 2:24-cv-00319-JRG, plaintiff Optiwave Semiconductor Corp. asserts Claims 1, 4, 6, and 11 of U.S. Patent No. 9,678,562 B2 against the following accused product lines manufactured and sold by defendant Lumicore Technologies, Inc.:
• LumiLink 400G-ZR+ coherent pluggable optical transceiver module
• LumiLink 800G-DR8 short-reach data-center optical transceiver module
The LumiEdge 1600G-LR is not accused of infringing the '562 Patent.
Infringement of the '562 Patent is alleged on a literal basis only. No infringement under the doctrine of equivalents is asserted with respect to the claims of the '562 Patent.
The key disputed claim construction term is "micro-channel heat sink." Plaintiff Optiwave Semiconductor Corp. proposes the construction: "a heat-dissipating structure containing channels with a hydraulic diameter of less than 1 mm." Defendant Lumicore Technologies, Inc. proposes the narrower construction: "a closed-loop liquid-cooling system with channels having a hydraulic diameter between 10 µm and 200 µm." The Benchmark teardown analysis (referenced in the Complaint) confirmed the presence of micro-channel structures in the accused LumiLink 400G-ZR+ and LumiLink 800G-DR8 products. The infringement claim chart maps the bonding methodology identified in the Benchmark teardown to the limitation of Claim 4.
ASSIGNMENT HISTORY / CHAIN OF TITLE
The chain of title for U.S. Patent No. 9,678,562 B2 is as follows:
1. Original Assignment — Inventors to Solara Optics, Inc.
Pursuant to employment agreements and invention assignment obligations, each of the named inventors — Dr. Henrik Vasquez, Dr. Mei-Ling Chow, and Dr. Arjun Deshmukh — assigned all right, title, and interest in the invention disclosed in Application No. 14/551,238 (which matured into U.S. Patent No. 9,678,562 B2) to Solara Optics, Inc., a California corporation with its principal place of business in San Jose, California. The original assignment was recorded with the United States Patent and Trademark Office. At the time of the invention and the filing of the patent application, all three inventors were employees of Solara Optics, Inc., serving as members of the company's photonic IC engineering team.
2. Asset Purchase Agreement — Solara Optics, Inc. to Optiwave Semiconductor Corp.
On June 15, 2018, Optiwave Semiconductor Corp. ("OWS") entered into an Asset Purchase Agreement ("APA") with Solara Optics, Inc. ("Solara Optics"), pursuant to which OWS acquired from Solara Optics substantially all of its intellectual property assets for a total purchase price of $34.5 million. The assets conveyed under the APA included a portfolio of twelve (12) United States patents and related continuation and continuation-in-part applications, including U.S. Patent No. 9,678,562 B2 (the '562 Patent) and the then-pending application that subsequently matured into U.S. Patent No. 10,234,847 B2 (the '847 Patent). The APA also conveyed associated patent prosecution files, inventor declarations, technical documentation, and all rights to enforce the acquired patents against past, present, and future infringers.
The assignment of the '562 Patent from Solara Optics, Inc. to Optiwave Semiconductor Corp. was recorded with the United States Patent and Trademark Office at Reel/Frame 046218/0534.
Gregory Falk, who served as Vice President of Engineering at Solara Optics at the time of the APA, played an instrumental role in the transaction, including identifying and cataloguing the intellectual property assets to be conveyed. Mr. Falk subsequently joined Optiwave Semiconductor Corp. and is designated as OWS's industry expert in the present litigation.
3. Dissolution of Solara Optics, Inc.
Solara Optics, Inc. was dissolved as a California corporation in 2020. The company is now defunct. All intellectual property rights formerly held by Solara Optics were conveyed to OWS prior to dissolution pursuant to the APA described above.
4. Current Owner.
The current owner of all right, title, and interest in U.S. Patent No. 9,678,562 B2 is:
Optiwave Semiconductor Corp. 4810 Bayside Technology Parkway, Suite 300 Santa Clara, CA 95054
Optiwave Semiconductor Corp. has standing to assert the '562 Patent in the present action.
PROSECUTION HISTORY SUMMARY
(Relevant Excerpts)
The following summary of the prosecution history of U.S. Patent No. 9,678,562 B2 is provided for the convenience of the Court and the parties. The complete file history is available from the United States Patent and Trademark Office and may be produced in discovery.